Cascode JFET-MOSFET Layout for Lower Switching Loss

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Solution Overview

Problem

Conventional semiconductor devices with cascode-connected JFET and MOSFET face challenges in reducing switching loss, particularly due to unoptimized gate voltage dependency and capacitance ratio.

Innovation Solution

The semiconductor device adjusts the gate voltage dependency and capacitance ratio of the JFET and MOSFET within specific ranges by connecting their source and drain electrodes, utilizing a JFET with a body diode and adjusting parameters such as the dosage or length of the adjustment region to minimize switching loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If conventional cascode-connected JFET and MOSFET are used without parameter optimization, then device configuration is simple, but switching loss is high

Engineering Contradiction:

Improveswitching lossVSAvoidconfiguration complexity

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by optimizing the gate voltage dependency and capacitance ratio within specific ranges. The gate voltage dependency is adjusted to satisfy |ΔVgJ/ΔVd| ≥ 0.001, and the capacitance ratio Cgd/Ciss is set between 0.01 and 0.1, which reduces switching loss while maintaining a relatively simple cascode configuration structure.

Inventive Principle:

Principle #35Parameter changes

2Loss of energy

If gate voltage dependency and capacitance ratio are optimized within specific ranges, then switching loss is reduced, but device design complexity increases

Engineering Contradiction:

Improveswitching lossVSAvoidparameter optimization complexity

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The patent defines specific parameter ranges (gate voltage dependency |ΔVgJ/ΔVd| ≥ 0.001 and capacitance ratio 0.01 ≤ Cgd/Ciss ≤ 0.1) that balance switching loss reduction with design feasibility. These quantified parameters provide clear design guidelines without requiring excessive optimization complexity.

Inventive Principle:

Principle #35Parameter changes

3Loss of energy

If JFET and MOSFET are cascode-connected with optimized parameters, then switching loss is reduced, but surge resistance may be affected

Engineering Contradiction:

Improveswitching lossVSAvoidsurge resistance

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent optimizes the gate voltage dependency parameter to satisfy |ΔVgJ/ΔVd| ≥ 0.001, which reduces switching loss while maintaining adequate surge resistance. The body diode configuration of the JFET further enhances surge resistance without compromising the switching loss reduction achieved through parameter optimization.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12575150B2Semiconductor device

Publication Date: 2026.03.10 DENSO CORP

AI summary

A semiconductor device includes a junction field effect transistor (JFET) including a source electrode, a drain electrode, and a gate electrode, and a metal oxide semiconductor field effect transistor (MOSFET) including a source electrode, a drain electrode, and a gate electrode. The JFET and the MOSFET are cascode-connected such that the source electrode of the JFET and the drain electrode of the MOSFET are electrically connected. A gate voltage dependency of the JFET or a capacitance ratio of a mirror capacitance of the MOSFET to an input capacitance of the MOSFET is adjusted in a predetermined range.