Cascode JFET Cell Layout for Overshoot and Ringing Suppression
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Solution Overview
Problem
JFETs in power electronics experience voltage overshoots and ringing when switching inductive loads, leading to parasitic turn-on and avalanche failure, and the addition of resistance in the gate path slows turn-on and turn-off speeds and increases switching loss.
Innovation Solution
Implementing JFET cells with different gate resistances and areas, configuring a fast cell with low-value resistance and a slow cell with high-value resistance in a cascode configuration to limit voltage overshoots while minimizing switching loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If resistance is added in the gate path of the MOSFET, then voltage overshoot is reduced, but turn-on and turn-off speeds slow down
Solution Approach 1:
The JFET device is divided into multiple cells (first plurality and second plurality) with different gate resistance values. This segmentation allows different portions of the device to contribute differently to voltage overshoot suppression, enabling fine-tuned control of the damping effect without uniformly slowing down the entire switching operation.
Solution Approach 2:
Different JFET cells are assigned different gate resistance values (first gate resistance vs. second gate resistance) to create local quality variations. This allows specific regions of the device to provide stronger or weaker damping effects based on local requirements, optimizing the balance between overshoot reduction and switching speed.
2Object-affected harmful factors
If resistance is added in the gate path of the MOSFET, then voltage overshoot is reduced, but switching loss increases
Solution Approach 1:
The JFET device segments the damping function across multiple cells with different gate resistances. This allows the voltage overshoot suppression to be distributed across different cells rather than concentrated in a single high-resistance path, reducing the overall impact on switching loss while maintaining effective overshoot control.
Solution Approach 2:
The invention changes the gate resistance parameter across different JFET cells to optimize performance. By having cells with different gate resistance values, the system can achieve effective voltage overshoot suppression while minimizing the increase in switching loss that would result from using a single high resistance value throughout.
3Strength
If high-voltage rated power switch is used in cascode configuration, then voltage rating is improved, but voltage overshoot and ringing occur during switching
Solution Approach 1:
The cascode power switch incorporates multiple JFET cells with different gate resistances to segment the voltage handling and damping functions. This segmentation allows the high-voltage rating to be maintained while differentiating the damping contribution of each cell, thereby reducing voltage overshoot and ringing during switching transitions.
Solution Approach 2:
Different JFET cells within the cascode configuration are assigned different gate resistance values to create local quality differences. This allows specific cells to provide enhanced damping during voltage transitions while others maintain optimal conducting properties, effectively reducing overshoot and ringing without compromising the overall voltage rating.
Data Source
AI summary
A power switch is disclosed. The power switch includes a metal-oxide semiconductor field-effect transistor (MOSFET) and a junction field effect transistor (JFET). The JFET is arranged in a cascode configuration with the MOSFET. The JFET includes a first plurality of JFET cells having a first gate resistance and a second plurality of JFET cells having a second gate resistance, wherein the second gate resistance is greater than the first gate resistance.