Cascode Level Shifter With Speed Enhancers for Wide Supply Range
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Solution Overview
Problem
Conventional level shifting circuits face issues with high switching time, poor performance at lower supply voltages, and lack of robustness due to conflicts between NMOS and PMOS transistors, floating N-wells, and metastability, especially in negative level shifters.
Innovation Solution
Incorporating a cascode switching module with speed enhancer modules that couple selected nodes to a defined voltage level to speed up charging or discharging operations, prevent floating conditions, and eliminate metastability, thereby enhancing switching speed and robustness across a wide range of supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional cascode switching module is used, then level shifting function is achieved, but switching time is high and switching currents are large
Solution Approach 1:
The patent introduces an intermediate voltage level (VINT) between VDD and VNEG, creating a two-stage switching process. The first stage switches between VDD and VINT, and the second stage switches between VINT and VNEG. This intermediary voltage level prevents direct conflict between PMOS and NMOS transistors, reducing switching time and short circuit current while maintaining the level shifting function.
Solution Approach 2:
The level shifting operation is segmented into two independent stages: first stage handling the transition from VDD to VINT, and second stage handling the transition from VINT to VNEG. Each stage uses dedicated transistors that are properly sized to avoid simultaneous conduction, thereby reducing switching time and power consumption.
2Adaptability or versatility
If conventional level shifter design is used, then basic level shifting is achieved, but performance deteriorates at lower VDD values
Solution Approach 1:
The patent changes the operating parameters by introducing an intermediate voltage level and reconfiguring the transistor sizing relationships. The transistors in the first stage are sized to operate efficiently at lower VDD, while the second stage handles the high voltage swing. This parameter change enables the circuit to maintain good performance across a wide supply voltage range including lower VDD values.
3Reliability
If conventional negative level shifter is used, then negative voltage generation is achieved, but design is not robust due to floating N-wells and metastability
Solution Approach 1:
The intermediate voltage level VINT serves as a mediator that prevents direct conflict between the pull-up PMOS and pull-down NMOS transistors. By routing signals through this intermediate level, the patent eliminates the floating N-well problem and metastability conditions that occur in conventional direct switching architectures.
Solution Approach 2:
The patent provides beforehand cushioning by ensuring that transistors are properly sized and biased before switching occurs. The intermediate voltage level acts as a buffer that prevents harmful floating conditions and metastability from developing, cushioning the circuit against these reliability issues before they can manifest.
Data Source
AI summary
The present invention discloses a fail-safe level shifter switching with high speed and operational for a wide range of voltage supply. The level shifter includes a cascode module, and one or more speed enhancer modules. The cascode module is receiving one or more input logic signal for generating a plurality of output signals with a reduced switching time. The speed enhancer modules are coupled to the cascode module for facilitating faster charging and discharging of nodes of the cascode module and improving the robustness and operating voltage range of cascode module.