Complementary Cascode LNA With Capacitive Coupling for Linearity
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Solution Overview
Problem
Existing low-noise amplifier (LNA) circuitries face challenges in maintaining low noise and linearity while operating at lower power supply voltages and smaller transistor sizes, which affects biasing and transistor operation.
Innovation Solution
The proposed LNA circuitry employs a dual cascode amplifier configuration with capacitive coupling between the transistors, allowing for separate DC and AC paths. This configuration maintains low power supply requirements while enhancing linearity by cancelling out distortion components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dual cascode amplifier configuration with capacitive coupling is used, then linearity is improved by cancelling distortion components, but device complexity increases
Solution Approach 1:
The patent combines two complementary cascode amplifiers into a single integrated circuit where the first cascode amplifier and second complementary cascode amplifier share common components and are coupled through capacitive coupling. This merging approach achieves distortion cancellation and improved linearity while managing the inherent complexity through systematic integration of the dual amplifier configuration.
2Object-affected harmful factors
If transistors are stacked in cascode configuration, then noise performance is improved, but the required supply voltage increases
Solution Approach 1:
The patent segments the cascode amplifier configuration into two separate complementary amplifiers rather than stacking all transistors in a single high-voltage path. Each cascode amplifier operates with its own biasing requirements, allowing the circuit to achieve low noise performance through the cascode topology while managing supply voltage requirements by distributing the voltage requirements across separate amplifier paths rather than stacking them all in series.
3Reliability
If complementary cascode amplifiers are used, then distortion cancellation is achieved, but biasing complexity increases at lower power supply voltages
Solution Approach 1:
The patent employs biasing circuitry that provides feedback mechanisms to automatically adjust and maintain proper operating points for both the first cascode amplifier and second complementary cascode amplifier. This feedback-based biasing system simplifies the operation of the complementary amplifiers by automatically compensating for variations and ensuring optimal biasing conditions without requiring manual adjustment, thereby reducing biasing complexity despite the dual amplifier configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual cascode amplifier configuration with capacitive coupling effectively reduces non-linear effects such as intermodulation distortion and harmonic distortion, while maintaining low power consumption and biasing requirements, thus improving the overall performance of the LNA circuitry.
Implementation Method 1
inputs of the first and second transistors are capacitively coupled such that the first and second transistors are connected at frequencies higher than a frequency characterising the capacitive coupling
Data Source
AI summary
A low-noise amplifier, LNA, circuitry for amplifying an input signal to an output signal; the circuitry comprising a first cascode amplifier and a second complementary cascode amplifier, respectively connected to a first load and a second load; wherein the first load and the second load are coupled and wherein the output signal is an output of the first or second cascode amplifier; wherein the first cascode amplifier comprises a first initial amplification stage and a first transistor; wherein the second cascode amplifier comprises a second initial amplification stage, and a second transistor, arranged in a common-gate configuration, in cascode with the second initial amplification stage and connected to the second load; and wherein inputs of the first and second transistors are capacitively coupled such that the first and second transistors are connected at frequencies higher than a frequency characterising the capacitive coupling.