Cascode LNA Distortion Compensation for Higher IIP3
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Solution Overview
Problem
Current high-frequency amplifier circuits, particularly Low Noise Amplifiers (LNAs), face challenges in achieving high Third Order Input Intercept Point (IIP3) performance due to distortion issues, which are exacerbated by carrier aggregation in radio communication systems.
Innovation Solution
The implementation of a distortion compensation circuit within the LNA, comprising diode-connected transistors and capacitors, which connects nodes between cascode-connected transistors to suppress third-order intermodulation distortion and improve IIP3 characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional LNA configuration is used, then the circuit structure is simple, but the IIP3 performance is insufficient due to distortion issues
Solution Approach 1:
A distortion compensation circuit is introduced as an intermediary component between the amplifier circuit and the load. This compensation circuit includes a third transistor connected to the drain of the first transistor and a fourth transistor connected to the source of the third transistor, which generates reverse distortion to cancel out the third-order intermodulation distortion produced by the amplifier circuit, thereby improving IIP3 performance without fundamentally changing the amplifier structure
Solution Approach 2:
The distortion compensation circuit performs preliminary anti-action by generating reverse distortion signals in advance to counteract the distortion that will be produced by the amplifier circuit. The third and fourth transistors are configured to produce a distortion signal that is opposite in phase to the intermodulation distortion, effectively canceling it out before it degrades the output signal quality
2Reliability
If distortion compensation circuitry is added to improve IIP3, then IIP3 performance increases by up to 16 dB, but device area and power consumption increase
Solution Approach 1:
The distortion compensation circuit uses transistors with specifically optimized local characteristics. The third transistor has a gate width Wg3 and the fourth transistor has a gate width Wg4, where Wg4 < Wg3. This local optimization of transistor dimensions allows the compensation circuit to generate the necessary reverse distortion while minimizing the current consumption and power usage of the compensation circuit itself
3Reliability
If distortion compensation circuitry is added to improve IIP3, then IIP3 performance increases by up to 16 dB, but device area increases
Solution Approach 1:
The distortion compensation circuit is nested within the existing LNA architecture by sharing power supply connections and integrating the third and fourth transistors in a cascoded configuration with the existing first and second transistors. The compensation circuit shares the same power supply voltage terminal and ground connections, allowing it to be embedded within the existing device footprint without requiring completely separate circuit blocks
Solution Approach 2:
The distortion compensation function is merged with the amplification function by using the same transistor stack for both purposes. The third transistor serves dual functions as part of both the compensation circuit and the signal path, while the fourth transistor provides both compensation and current control functions, thereby reducing the total device area required
Data Source
AI summary
Circuitry includes an amplifier circuit having a first transistor, an inductor, and a second transistor, and a distortion compensation circuit having a third transistor, a forth transistor, and a first capacitor. The first transistor is applied input signal. The inductor is connected to a source of the first transistor and grounded on another side. The second transistor has a source connected to a drain of the first transistor, a grounded gate and a drain connected to a power supply, and outputs an amplified signal. The third transistor has a drain and a gate connected to the drain, and is connected to the power supply on the drain. The fourth transistor has a drain and a gate connected to a source of the third transistor, and is grounded on a source. The first capacitor connects nodes between the drain of the first transistor and the source of the third transistor.