Cascode Semiconductor Module With Integrated Sensing and Self-Locking
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Solution Overview
Problem
Conventional power electronic systems face challenges in monitoring operating points and states of power semiconductors efficiently, particularly in ensuring minimal conduction and switching losses, and achieving self-locking characteristics for safety-relevant applications.
Innovation Solution
A cascode arrangement is designed with a substrate, a self-conducting semiconductor switch, and a low-voltage MOSFET, where the MOSFET and self-conducting semiconductor switch are electrically and thermally coupled via a connecting material, integrated with a sensor system to detect physical variables, enabling self-locking and reduced conduction losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If SiC-JFETs are used to achieve low conduction losses and simplified manufacturing, then conduction losses are reduced and manufacturing is simplified, but the devices are not self-locking and functional safety cannot be ensured
Solution Approach 1:
The patent combines a SiC-JFET with a Si-MOSFET in a cascode configuration to merge the advantages of both devices. The SiC-JFET provides low conduction losses and simplified manufacturing, while the Si-MOSFET contributes self-locking capability. The gate terminal of the JFET is connected to the source terminal of the MOSFET, creating a unified device that achieves both energy efficiency and functional safety.
2Reliability
If a cascode circuit is used to achieve self-locking capability, then functional safety is ensured, but the short-circuit time becomes excessively long
Solution Approach 1:
The patent modifies the electrical parameters of the cascode circuit by optimizing the gate-source voltage thresholds of both the JFET and MOSFET. By carefully selecting devices with appropriate voltage thresholds and configuring the gate connection, the circuit achieves self-locking with a controlled and reduced short-circuit time, balancing reliability requirements with time constraints.
3Reliability
If monitoring systems are added to ensure functional safety, then safety is improved, but device complexity increases
Solution Approach 1:
The cascode arrangement enables self-monitoring through the inherent electrical characteristics of the combined JFET-MOSFET structure. The gate connection between the two devices creates natural feedback mechanisms that allow the system to self-diagnose and self-protect without requiring additional external monitoring circuits, thereby maintaining functional safety while minimizing added complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The cascode arrangement achieves self-locking, low conduction losses, and simplified manufacturing, while allowing for accurate monitoring of physical variables, enhancing the reliability and efficiency of power semiconductor modules.
Implementation Method 1
both an electrical as well as a thermal coupling between the self-conducting semiconductor switch and the MOSFET being implemented via the connecting material
Implementation Method 2
the substrate being advantageously usable for dissipating heat generated by the cascode arrangement
Data Source
AI summary
A cascade arrangement and to a semiconductor module. The cascode arrangement includes: a substrate, a JFET, a MOSFET, and at least one sensor system. A drain terminal of the MOSFET is electrically connected to a source terminal of the JFET and a source terminal of the MOSFET is electrically connected to a gate terminal of the JFET. A first semiconductor layer in which the MOSFET is formed and a second semiconductor layer in which the JFET is formed, are situated stacked on top of one another via a connecting material. Both an electrical and a thermal coupling between the JFET and the MOSFET are implemented via the connecting material. The stacked semiconductor layers are situated on the substrate. The first semiconductor layer includes a first subarea in which the MOSFET is formed and at least one second subarea in which the at least one sensor system is formed.