Cascode Protected Negative Voltage Switching Circuit
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Solution Overview
Problem
Existing negative voltage switching technologies in semiconductor integrated circuits, such as those used in flash memory devices, face challenges in efficiently managing and switching both high and low negative voltages, particularly in preventing snapback and extending the negative input range while ensuring reliable operation.
Innovation Solution
The proposed solution involves a negative switch circuit design using NMOS and PMOS transistors in a triple well configuration with cascode protection, which includes separate P-wells and deep N-wells to reduce well resistance and prevent snapback, along with a negative cascode bias generator to adjust voltage levels for safe switching, enabling hot switching beyond the snapback limits of individual devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional negative voltage switching is used, then the circuit can switch negative voltages, but snapback occurs limiting the negative input range
Solution Approach 1:
The patent divides the switching function into multiple cascode stages (first cascode stage with transistor pair 20-22, second cascode stage with transistor pair 24-26). Each stage handles a portion of the voltage range, allowing the circuit to switch both high negative voltages (down to -9V) and low negative voltages (down to -0.25V) without snapback by segmenting the voltage handling responsibilities across stages.
Solution Approach 2:
The cascode transistors (20, 24) act as intermediary protection devices between the input negative voltage and the pass transistors (22, 26). These intermediary devices prevent snapback by controlling the voltage distribution and protecting the pass transistors from excessive voltage stress, enabling reliable switching across extended negative voltage ranges.
2Productivity
If high negative voltages are switched, then flash memory erase performance is improved, but gate aided drain breakdown risk increases
Solution Approach 1:
The cascode protection devices (20, 24) are positioned beforehand in the circuit to cushion and limit the voltage stress on pass transistors (22, 26) before high negative voltages can cause gate aided drain breakdown. This protective structure allows high negative voltages necessary for fast erase operations while preventing harmful breakdown effects.
3Reliability
If separate P-wells and deep N-wells are used, then well resistance is reduced and snapback is prevented, but device complexity increases
Solution Approach 1:
The patent implements separate P-wells and deep N-wells specifically in the cascode protection devices (20, 24) where voltage stress is highest, rather than throughout the entire circuit. This localized application of complex well structures provides snapback prevention where most needed while minimizing overall device complexity.
Data Source
AI summary
A double cascode protected switchable voltage source may be used to selectively provide positive or negative voltage sources, for example, to a flash memory. The positive supply may be connected through a PMOS pass device to a first cascode protection device. A negative supply may be connected through an NMOS pass device and an NMOS cascode protection device to an output. The circuits may be designed so that exceeding snapback limits and gate aided drain breakdown are less likely.