Cascode Output Circuit for Power-Down Spike Voltage Protection

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Solution Overview

Problem

Existing output circuits face destruction when a voltage higher than the withstand voltage of transistors is applied, particularly due to spike noise during power-down mode transitions, which can exceed the safe operating voltage of n-channel and p-channel field effect transistors.

Innovation Solution

The implementation of a semiconductor integrated circuit with two 1.65 V power supplies and a specific configuration of cascode and switch transistors, along with voltage generation circuits, ensures that no voltage higher than 1.8 V is applied to the transistors, preventing destruction by isolating intermediate nodes and using clip voltages to manage signal levels and prevent spike noise propagation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If transistors are used in output circuit without voltage protection, then circuit complexity is reduced, but transistor destruction occurs due to spike noise exceeding withstand voltage

Engineering Contradiction:
Improvecircuit complexityVSAvoidtransistor reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces intermediate nodes between power supply lines and transistor gates, controlled by switch transistors. These intermediaries isolate voltage spikes from reaching the transistor gates during power-down mode, preventing destruction while maintaining circuit functionality. The first and second intermediate nodes serve as buffer zones that decouple the power supply transitions from the sensitive transistor gates.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent activates switch transistors in advance during power-down mode to connect intermediate nodes to power supply lines before voltage spikes can propagate to transistor gates. This preliminary action ensures that when voltage transitions occur, the protective path is already in place, preventing spike noise from reaching and destroying the transistors.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If clip voltage circuits are added to protect transistors, then transistor reliability is improved, but device complexity increases

Engineering Contradiction:
Improvetransistor reliabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple functions into the cascode transistors and switch transistors. The cascode transistors serve both as voltage clipping elements and as part of the output drive circuitry. The switch transistors simultaneously control intermediate node connections and provide voltage clipping functionality. This merging reduces the need for separate protection circuits, balancing reliability improvement with acceptable complexity increase.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If intermediate nodes are isolated during power down, then voltage protection is achieved, but signal transmission capability is reduced

Engineering Contradiction:
Improvevoltage protectionVSAvoidsignal transmission capability
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent employs dynamic control of switch transistors that adjust the connectivity of intermediate nodes based on operating mode. During power-down mode, switch transistors activate to isolate intermediate nodes for protection. During normal operation, switch transistors deactivate to restore signal transmission paths. This dynamic switching ensures both protection during vulnerable transitions and full functionality during steady-state operation.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11791820B2Output circuit, transmission circuit, and semiconductor integrated circuit
Publication Date: 2023.10.17 SOCIONEXT INC
  • US11791820B2 patent drawing
  • US11791820B2 patent drawing
  • US11791820B2 patent drawing

AI summary

An output circuit includes: a first input transistor that is provided between a first power supply line and a first intermediate node; a second input transistor that is provided between a second intermediate node and a second power supply line; a first cascode transistor that is provided between the first intermediate node and an output node, and receives a first clip voltage from a first voltage generation circuit; a second cascode transistor that is provided between the output node and the second intermediate node, and receives a second clip voltage from a second voltage generation circuit; a first switch transistor that is provided between the first intermediate node and a gate of the first cascode transistor, and turns on during power down; and a second switch transistor that is provided between the second intermediate node and a gate of the second cascode transistor, and turns on during power down.