Cascode PA Output Stage With Switched-Bulk Biasing Against Snapback
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Solution Overview
Problem
High power power amplifiers (PAs) face challenges in handling large peak signal values due to low breakdown voltages in CMOS processes, requiring complex architectures and increased system costs, while bipolar implementations are costly and inefficient.
Innovation Solution
The implementation of a cascode configuration with switched-bulk biasing to minimize snapback effects and adaptively bias the output stage, using high voltage and low voltage FETs in series, with the bulk connected to ground during active operation to reduce voltage stress and prevent device breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If CMOS processes are used for power amplifier implementation, then manufacturing cost and availability are improved, but device breakdown voltage is reduced to 2-4V requiring complex architectures
Solution Approach 1:
The output stage is divided into multiple parallel segments (first output stage and second output stage), each handling a portion of the total output power. This segmentation allows each individual device to operate at lower voltage stress while collectively delivering high power output, resolving the contradiction between using low-voltage CMOS devices and achieving high power amplification.
Solution Approach 2:
Multiple parallel output stages are combined to achieve the required high output power. The first output stage and second output stage are merged in parallel configuration, where each stage contributes to the total output, allowing the system to overcome the individual device voltage limitation while maintaining CMOS manufacturing advantages.
2Strength
If segmented PA output stages are used to reduce peak voltage, then device voltage stress is reduced, but area and cost increase due to large power combiners
Solution Approach 1:
The patent extracts and eliminates the need for large external power combiners by integrating the combining function directly into the parallel output stage architecture. The current mirrors and load structures are designed to inherently combine the outputs of multiple parallel stages without requiring separate large-area combiner circuits, thus reducing the overall area while maintaining voltage stress benefits.
3Strength
If differential output stages are used to reduce voltage stress, then active device voltage stress is reduced, but area and complexity increase due to converters
Solution Approach 1:
Instead of converting between single-ended and differential configurations, the patent inverts the approach by directly implementing parallel single-ended output stages with current mirror coupling. This eliminates the need for complex differential converters while achieving the same voltage stress reduction benefit, simplifying the overall architecture.
4Power
If bipolar HBT processes are used to achieve high output power, then device breakdown voltage and power delivery are improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the operating parameters of CMOS devices, specifically optimizing the parallel stage configuration, current mirror ratios, and load impedance values to enable CMOS devices to deliver high power output comparable to bipolar HBT devices. By adjusting these parameters, the system achieves high power delivery using cost-effective CMOS manufacturing processes.
Data Source
AI summary
A power amplifier (PA) using switched-bulk biasing to minimize the risk of output stage snapback effect is disclosed. An adaptive biasing of the output stage prevents device breakdown while accommodating large voltage swings. These protection techniques can be applied to all types of cascode configurations of a PA, including single-ended, differential, quadrature, segmented and any combination thereto.