Cascode Power Device Packaging via Vertical GaN Stacking
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Solution Overview
Problem
Current packaging methods for cascode power electronic devices face challenges in reducing inductance, resistance, and thermal resistance, which limit power density and switching frequency improvements.
Innovation Solution
A packaging method involving a substrate with a pressure-sensitive adhesive layer, where gallium nitride semiconductor dies, diodes, and metal oxide semiconductor transistors are coated with photo-developing layers, copper plating is applied, and a heat sink is integrated, followed by peeling and cascading of package modules using blue tape to form a power electronic device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional packaging methods are used for cascode power electronic devices, then the package structure is simple and easy to manufacture, but the inductance, resistance, and thermal resistance of connecting wires are high, limiting power density and switching frequency
Solution Approach 1:
The device is divided into multiple separate chips (GaN HEMT chip and MOSFET chip) that are vertically stacked and interconnected through conductive vias. This segmentation allows each chip to be optimized independently while reducing parasitic elements through minimized inter-chip connection paths, directly addressing the contradiction by enabling high power density through modular architecture.
Solution Approach 2:
The packaging transitions from a planar horizontal layout to a vertical three-dimensional stacked configuration. By stacking chips vertically and using through-silicon vias for interconnection, the design minimizes current path length and parasitic inductance while improving thermal dissipation, thus achieving high power density without excessive manufacturing complexity.
2Productivity
If connecting wires with high inductance and resistance are used, then the package structure is simple, but the power density and switching frequency cannot be improved
Solution Approach 1:
The design extracts and eliminates traditional wire bonds and lead frames that introduce high parasitic inductance and resistance. Instead, direct copper metallization and conductive vias are used to create low-inductance current paths between chips and external terminals, simultaneously improving power density and electrical performance reliability.
Solution Approach 2:
Traditional mechanical wire bonding is replaced with direct metallurgical bonding through conductive vias and copper traces. This substitution eliminates the mechanical connections that introduce high parasitic elements, achieving both high power density through reduced inductance and improved electrical reliability through direct metal-to-metal contact.
3Temperature
If traditional packaging structures are used, then manufacturing is easier, but thermal resistance is high and heat dissipation is poor
Solution Approach 1:
The packaging structure merges the electrical interconnection function with the thermal management function through integrated copper metallization and heat sink attachment. The same copper layers that provide low-inductance electrical paths also serve as thermal conduction paths to the heat sink, achieving effective heat dissipation while maintaining manufacturing simplicity through multi-functional integration.
Solution Approach 2:
The package uses composite material structures including copper-molybdenum heat sink attachments, ceramic substrates with high thermal conductivity, and thermally conductive underfills. These composite materials provide superior thermal management capabilities while maintaining compatibility with existing manufacturing processes through standardized material systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces inductance, resistance, and thermal resistance, enhancing power density and switching frequency in cascode power electronic devices.
Implementation Method 1
coating a first photo-developing layer on the pressure sensitive adhesive layer... exposing and developing a first surface of the first photo-developing layer
Implementation Method 2
plating copper on the exposed and developed area to form a copper plating layer
Data Source
AI summary
The present invention provides a packaging method and a packaging structure for a cascode power electronic device, in which a hetero-multiple chip scale package is used to replace the traditional die bonding and wire bonding packaging method. The cascode power electronic device can reduce the inductance resistance and thermal resistance of the connecting wires and reduce the size of the package; and increase the switching frequency of power density. The chip scale package of the present invention uses more than one gallium nitride semiconductor die, more than one diode, and more than one metal oxide semiconductor transistor. The package structure can use TO-220, quad flat package or other shapes and sizes; the encapsulation process of the traditional epoxy molding compounds can be used in low-power applications; and the encapsulation process of ceramic material can be used in high-power applications.