Complementary Cascode Power Amplifier for 5G Linearity
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Solution Overview
Problem
Power amplifiers in 5G systems face challenges with higher linearity requirements for high-order modulation and reliability issues such as hot carrier injection, time-dependent dielectric breakdown, and bias temperature instability, which affect their performance and lifespan.
Innovation Solution
The proposed power amplifier structure incorporates complementary transistors connected in series with inductors to reduce parasitic capacitance, enhance power output, and improve reliability, featuring a cascode amplifier configuration with p-type and n-type transistors and transformers to split and combine signals effectively, thereby mitigating AM-PM distortion and increasing linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional power amplifier structures are used, then device complexity is reduced, but linearity and reliability deteriorate due to parasitic capacitance and HCI effects
Solution Approach 1:
The power amplifier is segmented into multiple stages with complementary transistors (first transistor of first type, second transistor of second type) connected in series. Each transistor stage is independently biased and controlled, allowing separate optimization of linearity and power output. This segmentation reduces the impact of parasitic capacitance at any single node while maintaining overall device reliability.
Solution Approach 2:
Inductors are introduced as intermediary elements connected to intermediate nodes between the complementary transistors. These inductors serve as impedance transformation elements that cancel parasitic capacitance effects and improve power transfer. The inductors act as mediators between the transistor stages and the load, enhancing both linearity and reliability without requiring complete restructuring of the amplifier.
2Power
If higher power output is achieved, then power loss increases, but this leads to increased heat generation and reduced reliability
Solution Approach 1:
The patent employs parameter changes by introducing inductors with specific impedance values at intermediate nodes to optimize power transfer. The inductance values are carefully selected to cancel parasitic capacitance effects at operating frequencies, improving power efficiency. Additionally, the bias conditions of complementary transistors are optimized to operate in regions that maximize power output while minimizing dissipative losses.
Solution Approach 2:
The power amplifier uses composite transistor configurations combining p-type and n-type transistors in a complementary arrangement. This composite structure allows the amplifier to utilize the advantageous characteristics of both transistor types, achieving higher efficiency and reduced power loss compared to single-type transistor amplifiers. The complementary configuration enables better control of current flow and reduces unnecessary power dissipation.
3Manufacturing precision
If linearity is improved for high-order modulation, then device complexity increases due to additional circuit elements
Solution Approach 1:
The patent implements dynamic biasing schemes where the bias conditions of complementary transistors are adjusted based on operating conditions to maintain optimal linearity. The inductors at intermediate nodes provide dynamic impedance transformation that adapts to signal variations, improving linearity without requiring static complex circuit topologies. This dynamic approach allows high-order modulation support with moderate circuit complexity.
4Loss of energy
If parasitic capacitance is reduced, then power transfer efficiency improves, but this requires additional inductive elements increasing device complexity
Solution Approach 1:
Instead of uniformly adding inductive elements throughout the amplifier, the patent applies inductors selectively at specific intermediate nodes where parasitic capacitance has the most detrimental effect on power transfer. This localized approach targets the most critical capacitance nodes (such as drain-gate capacitances of power transistors) with inductive cancellation, achieving significant power loss reduction with minimal additional components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the power amplifier's linearity, reliability, and modulation quality, reducing power loss and increasing the overall performance while maintaining lower supply voltage levels, thus addressing the reliability and linearity challenges in 5G systems.
Implementation Method 1
The inductor is configured to reduce or cancel the parasitic capacitance at the connecting node
Implementation Method 2
The inductor is configured to reduce or cancel the parasitic capacitance at the intermediate node, which can decrease power loss
Data Source
AI summary
A power amplifier structure includes at least one power amplifier circuit. The power amplifier circuit includes a transistor of a first type connected in series with a transistor of a second type connected between the same voltage supply. In a non-limiting nonexclusive example, an n-type transistor is connected in series with a p-type transistor connected between Vdd. The power amplifier structure can include two amplifier circuits configured in a differential amplifier structure. The differential amplifier structure includes two amplifier circuits operably connected in parallel between the same voltage supply.