Self-Biased Cascode Reference Voltage Generator Circuit
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Solution Overview
Problem
Conventional reference voltage circuits for passive RFID tags require large currents and physical area, consuming a significant proportion of the available resources and failing to provide a stable voltage across varying temperatures.
Innovation Solution
A reference voltage generator circuit using a self-biased cascode connection of MOSFET transistors with a current source, where the bulk terminal of the first transistor is connected to its source terminal, allowing for a high power supply rejection ratio and temperature-independent reference voltage generation, utilizing minimal current and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bandgap reference voltage techniques are used, then a stable reference voltage can be generated, but large currents (∼1μA) are required and large physical area (∼10000μm²) is consumed
Solution Approach 1:
The patent changes the operating parameters of the reference voltage circuit by using a different transistor configuration (cascode connection with bulk terminal connected to source) and operating point selection that enables stable reference voltage generation at much lower currents (25nA or less) and smaller areas, fundamentally altering the performance parameters compared to conventional bandgap references
Solution Approach 2:
The reference voltage generator uses self-biasing through the cascode connection where the bulk terminal of the first transistor is connected to its source terminal, creating automatic temperature compensation and stable operation without requiring large external bias currents or complex additional circuitry
2Reliability
If conventional bandgap reference voltage techniques are used, then a stable reference voltage can be generated, but large currents (∼1μA) are required and large physical area (∼10000μm²) is consumed
Solution Approach 1:
The patent fundamentally changes the current consumption parameter by using a cascode transistor configuration with self-biasing that operates stably at 25nA or less, compared to the ∼1μA required by conventional bandgap references, achieving both low power and high stability
Solution Approach 2:
The self-biasing cascode connection automatically regulates the operating point and provides temperature compensation without requiring large bias currents, enabling the circuit to serve itself with minimal external current input while maintaining stable reference voltage output
3Ease of manufacture
If the bulk terminal is connected to a supply voltage rail, then the circuit is simpler to design, but the power supply rejection ratio is lower and the reference voltage is more dependent on supply voltage
Solution Approach 1:
The bulk terminal connection acts as an intermediary that isolates the reference voltage generation from supply voltage variations by connecting the bulk terminal to the source terminal rather than to the supply rail, creating an intermediate reference point that improves power supply rejection while maintaining design simplicity
4Reliability
If a reference voltage circuit is designed for high stability across temperature, then temperature compensation mechanisms are required, but the circuit complexity increases
Solution Approach 1:
The cascode connection with bulk terminal connected to source creates self-biasing that automatically compensates for temperature effects through the inherent characteristics of the transistor configuration, eliminating the need for complex external temperature compensation circuits while maintaining high temperature stability
Solution Approach 2:
The patent changes the biasing parameters and transistor configuration to exploit the natural temperature characteristics of the cascode connection, achieving temperature stability through parameter optimization rather than complex compensation circuitry
Data Source
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AI summary
A reference voltage generator circuit (100) is disclosed, comprising a first transistor (101) having a first channel type and a second transistor (102) having a second channel type. A current source (104) is connected to a source terminal of the first transistor (101). A drain terminal of the second transistor (102) is connected to a drain terminal of the first transistor (101). The reference voltage generator circuit (100) further comprises a third transistor (103) having the second channel type, wherein a drain terminal of the third transistor (103) is connected to a source terminal of the second transistor (102). A node between the source terminal of the second transistor (102) and the drain terminal of the third transistor (103) is connected to a gate terminal of the first transistor (101). A connection for a reference voltage (Vrc) is provided between the current source (104) and the source terminal of the first transistor (101).