Cascode Amplifier Bias Circuit for Supply-Variant CMOS RF Stages
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Solution Overview
Problem
Silicon-based CMOS cascode amplifier circuits face challenges in designing bias circuits that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, while also compensating for poor output resistance characteristics and adapting to changing RF electrical environments.
Innovation Solution
The implementation of a cascode reference circuit with a closed loop bias control circuit that dynamically adjusts the gate bias voltage to maintain a consistent current multiple, accommodating arbitrary supply voltage variations and improving output resistance by matching drain and gate voltages across stages, and incorporating a stack of series-connected CMOS devices to distribute RF voltage swing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a cascode amplifier uses silicon-based CMOS devices with short channel lengths to achieve fast RF response, then speed is improved, but output resistance characteristics deteriorate due to poor output resistance
Solution Approach 1:
The amplifier is divided into multiple stacked transistor stages (common source stage and common gate stage) rather than using a single transistor. This segmentation allows the short-channel transistors to operate in a cascode configuration where the overall output resistance is the product of individual stage output resistances, compensating for the poor output resistance of individual short-channel devices while maintaining fast RF response.
Solution Approach 2:
The patent introduces an additional voltage control dimension by implementing a closed-loop bias control circuit that dynamically adjusts gate bias voltages. This adds a control dimension to compensate for voltage variations and maintain stable output resistance characteristics, transforming a static poor performance parameter into a dynamically controllable one.
2Adaptability or versatility
If the DC supply voltage is actively modified to optimize operation at different power levels, then adaptability is improved, but bias circuit stability deteriorates due to supply voltage variations
Solution Approach 1:
A closed-loop bias control circuit is implemented that continuously monitors the supply voltage and dynamically adjusts the gate bias voltages of the stacked transistors in response. This feedback mechanism compensates for supply voltage variations, maintaining stable bias conditions and output resistance characteristics even when the DC supply voltage is actively modified for different power levels.
Solution Approach 2:
The bias circuit transitions from a static configuration to a dynamic one where gate bias voltages are continuously adjusted based on supply voltage conditions. The closed-loop control enables the bias points to adapt dynamically to changing supply voltages, maintaining stability throughout the power level optimization range.
3Strength
If stacked transistor configuration is used to overcome breakdown voltage liability, then voltage tolerance is improved, but device complexity increases
Solution Approach 1:
The stacked transistor configuration serves multiple functions simultaneously: it increases breakdown voltage tolerance by distributing voltage stress across multiple devices, improves output resistance through the cascode effect, and provides additional control nodes for bias adjustment. This multi-functionality justifies the increased device complexity by delivering multiple performance benefits from a single architectural choice.
Data Source
AI summary
Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.