Cascode Circuit Schottky Diode Capacitor Integration
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Solution Overview
Problem
Conventional cascode circuits in the radiofrequency band face variations in transistor characteristics due to process-sensitive Schottky junctions, leading to deviations in optimum capacitance values, increasing manufacturing costs and chip area requirements.
Innovation Solution
A cascode circuit utilizing a Schottky barrier diode as a capacitor, formed in proximity to the transistor, which adjusts capacitance in tandem with the transistor's active layer concentration variations, reducing the number of process steps and chip area, thereby minimizing cost and optimizing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a MIM capacitor is used in conventional cascode circuits, then the capacitance value can be stabilized, but the chip area increases and manufacturing cost increases
Solution Approach 1:
The patent merges the capacitor function with the Schottky barrier diode structure by utilizing the depletion layer of the diode as the capacitive element. This integration eliminates the need for separate MIM capacitor structures, thereby reducing chip area while maintaining capacitance stability through the process-insensitive depletion layer mechanism.
Solution Approach 2:
The Schottky barrier diode structure serves dual functions: as a rectifying element and as a capacitor. The depletion layer formed in the diode structure provides the necessary capacitive function, allowing the same structural elements to fulfill multiple circuit requirements without increasing chip area.
2Speed
If process-sensitive Schottky junctions are used in transistors, then high-frequency performance is achieved, but variations in transistor characteristics increase
Solution Approach 1:
The patent changes the operating parameter regime by utilizing the depletion layer width as the controlling parameter for capacitance instead of relying on precise Schottky barrier potential differences. The depletion layer width can be controlled by bias voltage, allowing the circuit to maintain optimal performance despite variations in Schottky junction characteristics caused by process variations.
3Manufacturing precision
If the number of process steps is increased to form MIM capacitors, then capacitance value can be stabilized, but manufacturing cost increases
Solution Approach 1:
The capacitor function is merged into the existing Schottky barrier diode fabrication process. The depletion layer capacitance is formed simultaneously with the diode structure during the same epitaxial growth and doping processes, eliminating the need for additional MIM capacitor fabrication steps and associated mask processes, thereby reducing manufacturing cost while maintaining capacitance stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution limits variations from the optimum operating capacitance and reduces manufacturing costs by integrating the Schottky barrier diode within the transistor formation process, maintaining capacitance stability while minimizing chip area and increasing chip density.
Implementation Method 1
the value of the MIM capacitor becomes different from the optimum value of C1... causes variations in transistor characteristics include variations in operating layer forming processes... while Cgs is determined generally by the depletion layer width during operation
Implementation Method 2
a Schottky barrier diode having its anode connected to the source of the first FET and its cathode connected to the gate of the second FET... when a gate is formed, Schottky characteristic parameters including the Schottky barrier potential difference Φb change easily depending on process conditions
Implementation Method 3
The capacitance C1 of the capacitor 3 and the resistance values R1 and R2 of the resistors 4 and 5 for determining the gate voltage of the second FET 2 are optimized... It is known that the optimum value of the capacitance value C1 of the capacitor 3 is as expressed by the following expression
Data Source
AI summary
A cascode circuit in which two field effect transistors (“FET”) are connected in cascode has a first FET having its source grounded, a second FET having its source connected to the drain of the first FET, and a Schottky barrier diode having an anode connected to the source of the first FET and a cathode connected to the gate of the second FET.