Cascode SiC-JFET and Si-MOSFET Switching Speed Control
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Solution Overview
Problem
Hybrid power devices formed of cascode-connected normally-on type SiC-JFET and normally-off type Si-MOSFET face issues with resonance and increased switching loss due to the existing resistor-based solutions that either suppress resonance or increase switching loss.
Innovation Solution
A control circuit with a speed regulating resistor and a capacitor connected in parallel between the gate of the SiC-JFET and the source of the Si-MOSFET, allowing for variable switching speeds during different stages of the switching period to control resonance and switching loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a resistor is connected between the gate of the SiC-JFET and the source of the Si-MOSFET to lower switching speed, then resonance is suppressed, but switching loss increases
Solution Approach 1:
The patent applies the dynamics principle by making the resistance value variable rather than fixed. The resistance between the gate of SiC-JFET and source of Si-MOSFET is dynamically adjusted based on the switching state: during turn-on, a lower resistance enables faster switching to reduce switching loss; during turn-off, a higher resistance suppresses resonance. This dynamic adjustment resolves the contradiction between suppressing resonance and minimizing switching loss.
Solution Approach 2:
The patent employs parameter changes by varying the resistance value according to different operational phases. The control circuit changes the resistance parameter from a low value during turn-on to a high value during turn-off, optimizing performance for each phase. This parameter variation allows the system to achieve both fast switching (low loss) and resonance suppression without compromise.
2Loss of energy
If the switching speed is increased to reduce switching loss, then switching loss decreases, but resonance occurs and transient high voltage damages the Si-MOSFET
Solution Approach 1:
The patent uses dynamics to adjust the resistance value based on the switching phase. During turn-on, low resistance enables high switching speed to minimize switching loss. During turn-off, high resistance limits switching speed to prevent resonance and transient voltage spikes. This dynamic control resolves the contradiction between fast switching and resonance prevention.
Solution Approach 2:
The control circuit performs preliminary action by pre-setting the resistance value before switching occurs. Before turn-on, the resistance is set to a low value to prepare for fast switching. Before turn-off, the resistance is set to a high value to prevent resonance. This preliminary configuration ensures optimal performance while avoiding harmful effects.
3Loss of energy
If the gate voltage of SiC-JFET is maintained high to maintain fast switching speed, then switching loss is reduced, but the voltage change in negative direction increases
Solution Approach 1:
The patent applies dynamics by making the gate voltage control flexible and variable. Instead of maintaining a constantly high gate voltage, the control circuit dynamically adjusts the gate voltage level based on the switching phase. During turn-on, high gate voltage enables fast switching; during turn-off, reduced gate voltage prevents excessive negative voltage change. This dynamic control resolves the contradiction between maintaining fast switching and controlling voltage changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively controls switching speed to minimize resonance and switching loss by providing high initial current for fast switching and reducing current later to stabilize operation, thereby optimizing the performance of the hybrid power FET.
Implementation Method 1
A control circuit with a speed regulating resistor and a capacitor connected in parallel between the gate of the SiC-JFET and the source of the Si-MOSFET
Data Source
AI summary
A hybrid power device is formed of a normally-on type SiC-JFET and a normally-off type Si-MOSFET, which are connected in cascode with a source of the SiC-JFET and a drain of the Si-MOSFET being connected to each other thereby forming a hybrid power FET. A gate of the SiC-JFET and a source of the Si-MOSFET are connected via a switching speed regulating resistor. A capacitor is connected to the switching speed regulating resistor in parallel to control a switching speed to a first speed in a former part of the switching period of the hybrid power FET and to a second switching speed in a latter part of the switching period. The second switching speed is lower than the first switching speed.