Cascode SiC JFET-MOSFET Switching for Low On-Resistance and SCWT
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Solution Overview
Problem
Existing power switching devices face challenges in achieving low on-resistance while maintaining sufficient short circuit withstand time (SCWT), often requiring larger die sizes and increased costs, and quick responses to short circuits can lead to false alarms and system instability.
Innovation Solution
A cascode switching circuit using a normally-on silicon carbide JFET and a normally-off silicon MOSFET, with a gate driver circuit that applies a positive bias under normal conditions to reduce on-resistance and a negative bias during short circuits to extend SCWT.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the on-resistance of a cascoded switch is reduced for a given application, then conduction loss decreases and efficiency improves, but the die size increases and cost increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the gate-to-source voltage of the normally-on transistor based on operating conditions. During normal operation, a first gate-to-source voltage is applied to optimize on-resistance and reduce conduction losses. During short circuit conditions, a second (different) gate-to-source voltage is applied to extend withstand time. This dynamic parameter adjustment resolves the contradiction by allowing the device to achieve low on-resistance without permanently increasing die size.
Solution Approach 2:
The patent implements dynamics by transitioning the normally-on transistor between different conduction states through controlled gate voltage adjustment. The transistor operates in a normally-on state during normal conditions and can be dynamically switched to a higher resistance state during short circuits. This dynamic operation allows the system to achieve low conduction losses during normal operation while maintaining the capability to withstand short circuits without requiring permanently larger die size.
2Reliability
If a quick response to short circuit is implemented, then protection is improved, but false alarms increase and system stability deteriorates
Solution Approach 1:
The patent applies preliminary anti-action by pre-configuring the normally-on transistor to be in a conducting state before short circuit conditions occur. This allows the device to quickly respond to short circuits by already having the appropriate conduction path established, reducing response time while maintaining system stability through controlled voltage adjustment rather than abrupt switching.
Solution Approach 2:
The patent uses parameter changes to differentiate between normal operation and short circuit conditions by adjusting the gate-to-source voltage of the normally-on transistor. During normal operation, one voltage level is maintained for optimal performance. Upon detecting a short circuit, the voltage is changed to a different level that extends the withstand time. This controlled parameter change allows quick response to faults while avoiding false alarms that would result from abrupt or inappropriate switching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves lower conduction losses and higher efficiency under normal conditions, while extending SCWT to prevent false alarms and protect the system from short circuit damage.
Implementation Method 1
The gate driver circuit may be configured to apply a positive bias voltage at a respective gate terminal of the normally-on transistor under a normal operating condition to thereby reduce an on-resistance of the normally-on transistor
Implementation Method 2
The gate driver circuit may also be configured to apply a negative bias voltage at the respective gate terminal of the normally-on transistor under a short circuit condition to thereby extend a short circuit withstand time (SCWT) of the normally-on transistor
Data Source
AI summary
A power switching device is disclosed. The power switching device includes a cascode switching circuit comprising a normally-on transistor and a normally-off transistor provided in a cascode topology. The power switching device also includes a gate driver circuit configured to apply a positive bias voltage at a respective gate terminal of the normally-on transistor under a normal operating condition, and to apply a negative bias voltage at the respective gate terminal of the normally-on transistor under a short circuit condition.