GaN-SiC Cascode Switch with Gate Clamp Circuit
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Solution Overview
Problem
GaN power transistors, being depletion mode and normally-on, cannot be directly used in circuits designed for MOSFETs without significant modifications, and their use in cascode configurations with silicon MOSFETs leads to reliability issues due to avalanche and gate isolation breakdowns.
Innovation Solution
A cascode transistor circuit is designed with a gallium nitride or silicon carbide field effect transistor and a silicon MOSFET, where a clamp circuit is introduced between the source and gate of the GaN/SiC FET to prevent avalanche and gate isolation breakdowns, using a diode circuit to limit voltage and ensure safe operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a GaN power transistor is used in a cascode configuration with a silicon MOSFET, then the device can be used in circuits designed for MOSFETs and existing gate drivers can be used, but avalanche and gate isolation breakdown occur due to high voltages, reducing reliability
Solution Approach 1:
A clamp circuit is introduced as an intermediary protective element between the GaN FET and the silicon MOSFET. The clamp circuit includes a clamp transistor, clamp resistor, and clamp capacitor that work together to limit voltage spikes and prevent avalanche breakdown in the silicon MOSFET and gate isolation breakdown in the GaN FET, thereby maintaining reliability while preserving compatibility with standard MOSFET circuits
Solution Approach 2:
The clamp circuit is configured to activate before dangerous voltage levels can cause damage. The clamp transistor and capacitor provide prior cushioning by capturing and dissipating voltage spikes before they can propagate to the GaN FET gate or cause avalanche in the silicon MOSFET, preventing reliability issues before they occur
2Adaptability or versatility
If additional layers are introduced in the layer stack to make the device normally-off, then the device becomes interchangeable with MOSFETs, but device performance is penalized
Solution Approach 1:
The system is segmented into two separate components: a GaN FET layer stack optimized for high power performance and a silicon MOSFET layer stack optimized for normally-off operation. This segmentation allows each component to maintain its optimal performance characteristics while working together in a cascode configuration, avoiding the performance penalty that would result from adding layers to the GaN stack
3Ease of operation
If the low voltage rated power MOSFET is used in the cascode configuration, then the circuit can operate at lower voltages, but the MOSFET is not protected from avalanche due to high drain-source voltage
Solution Approach 1:
The clamp circuit serves as a protective intermediary between the high voltage GaN FET and the low voltage silicon MOSFET. It monitors and limits the drain-source voltage across the silicon MOSFET, preventing avalanche breakdown while allowing the MOSFET to operate at its rated lower voltage, thus maintaining both ease of operation and reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The clamp circuit enhances the reliability and performance of the cascode switch by preventing avalanche currents and gate isolation breakdowns, allowing the use of lower voltage rated MOSFETs, reducing chip size, and increasing switching speed, making it suitable for various power conversion applications.
Implementation Method 1
preventing avalanche through the low voltage silicon MOSFET due to high drain-source voltages, and preventing avalanche or gate isolation breakdown of the GaN/SiC field effect transistor due to high source-gate voltages
Data Source
AI summary
A cascoded power semiconductor circuit has a clamp circuit between the source and gate of a gallium nitride or silicon carbide FET to provide avalanche protection for the cascode MOSFET transistor.