Cascode Switching Circuit With JFET Forward Bias for Lower ON-Resistance
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Solution Overview
Problem
Existing cascode switches face challenges in achieving low ON-state resistance and high saturation current capability without increasing die size and cost.
Innovation Solution
A cascode switching circuit comprising a JFET and MOSFET in a cascode topology, with a gate driver, current source, voltage clamp, and optional capacitor and resistor configurations to manage gate biasing and switching, reducing ON-state resistance and enhancing surge current capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the ON-state resistance of a cascode switch is reduced for a given application, then power loss and heat generation are limited, but die size and cost increase
Solution Approach 1:
The patent applies parameter changes by forward-biasing the gate-source junction of the JFET to reduce its ON-state resistance. By changing the electrical parameter (gate-source voltage) from zero or reverse bias to forward bias, the resistance decreases significantly, reducing power loss without requiring a larger die size. The circuit uses a current source and voltage clamp to control this parameter change.
2Power
If the saturation current of a cascode switch is increased for a given application, then surge current capability is improved, but die size and cost increase
Solution Approach 1:
The patent uses parameter changes to increase saturation current by forward-biasing the JFET gate-source junction. This parameter change allows the JFET to operate in a region with higher current capability. The cascode configuration with the MOSFET further enhances the saturation current while maintaining a compact structure, avoiding the need for larger die size.
3Loss of energy
If a current source is used to forward bias the JFET gate-source junction, then ON-state resistance is reduced, but circuit complexity increases
Solution Approach 1:
The patent applies multi-functionality by designing the gate driver circuit to perform multiple functions: it drives the MOSFET gate, provides forward bias to the JFET gate-source junction through a current source, and includes a voltage clamp to limit the JFET gate voltage. This integrated approach reduces overall circuit complexity compared to separate circuits for each function.
Solution Approach 2:
The patent uses an intermediary element (the current source coupled with voltage clamp) to mediate between the gate driver output and the JFET gate. This intermediary provides the necessary forward bias current while protecting the JFET gate from excessive voltage, simplifying the overall control architecture.
4Reliability
If a voltage clamp is added to prevent JFET gate voltage from exceeding clamp threshold, then device reliability is improved, but circuit complexity increases
Solution Approach 1:
The patent applies beforehand cushioning by incorporating a voltage clamp (such as a Zener diode) that preemptively limits the JFET gate voltage to a safe threshold level. This protective element is always present in the circuit, preventing voltage excursions before they can cause damage, thereby improving reliability without requiring complex control logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces ON-state resistance and increases surge current capability while maintaining a compact die size and cost efficiency.
Implementation Method 1
a current source coupled between the gate-driver output and the gate of the JFET and configured to forward bias a gate-source junction of the JFET when the cascode device is in an ON-state
Implementation Method 2
a voltage clamp coupled to the gate of the JFET and configured to prevent a gate voltage of the JFET from exceeding a clamp threshold. In some examples, the voltage clamp comprises a Zener diode
Data Source
AI summary
A cascode switching circuit is disclosed. The cascode switching circuit includes a cascode device comprising a JFET and a MOSFET coupled in a cascode topology. The cascode switching circuit further includes a gate driver having a gate-driver input configured to receive a switching input signal and a gate-driver output coupled to a gate of the MOSFET and configured to switch the MOSFET between a MOSFET ON-state and a MOSFET OFF-state based on the switching input signal. In addition, the cascode switching circuit includes a current source coupled between the gate-driver output and the gate of the JFET and configured to forward bias a gate-source junction of the JFET when the cascode device is in an ON-state.


