Cascode Transistor Circuit for High Output Resistance Testing
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Solution Overview
Problem
Existing methods for measuring output resistance of a device under test (DUT) are limited in accuracy, particularly when the output resistance exceeds 1 mega-ohm, leading to inconsistent and imprecise measurements due to the Miller effect and the inability to isolate input and output signals effectively.
Innovation Solution
A cascode transistor arrangement is used, comprising two cascode transistors with opposite dopant types, which isolates the input from the output, increasing measurement accuracy and bandwidth, allowing for a wider range of DUTs to be tested and enabling the measurement of higher output resistances by adding additional transistors in series, thereby reducing the Miller effect and enhancing measurement precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single transistor is used for measurement, then the device complexity is low, but the measurement precision deteriorates when output resistance exceeds 1 mega-ohm
Solution Approach 1:
The measurement system is segmented into multiple cascode transistor stages (two-stage or four-stage arrangements) to divide the measurement function across multiple components, enabling accurate measurement of high output resistances by isolating different measurement ranges for different resistance levels
Solution Approach 2:
Cascode transistors are introduced as intermediary elements between the DUT and measurement equipment, with their gates connected to specific potentials to isolate input and output signals and eliminate the Miller effect, thereby enabling accurate high-impedance measurements
2Measurement precision
If output resistance measurement is performed without isolation, then the device complexity is low, but the measurement precision deteriorates due to the Miller effect
Solution Approach 1:
Cascode transistors serve as intermediary isolation structures, with their gates connected to fixed potentials to electrically isolate the input and output nodes of the measurement system, thereby eliminating the Miller effect and enabling accurate measurement of high output resistances
Solution Approach 2:
The isolation function is segmented across multiple cascode stages, where each stage provides additional isolation and extends the measurable output resistance range, with two-stage arrangements measuring up to 3,000 mega-ohms and four-stage arrangements measuring up to 28 giga-ohms
3Measurement precision
If a fixed bias current is used, then the ease of operation is high, but the measurement precision deteriorates for high output resistance devices
Solution Approach 1:
The bias current parameter is optimized for each measurement configuration, with specific current values selected for each cascode stage to ensure accurate measurement across different output resistance ranges while maintaining operational simplicity through automated current control
Data Source
AI summary
An integrated circuit (IC) includes a first transistor having a first dopant type and a second transistor having a second dopant type opposite to the first dopant type. The first transistor includes a first terminal configured to receive a current, a second terminal connected to a node, and a first gate, and the second transistor includes a first terminal connected to a device under test (DUT), a second terminal connected to the node, and a second gate. Each one of the first gate, the node, or the second gate is capable of receiving a first voltage from a first voltage source simultaneously with another one of the first gate, the node, or the second gate receiving a second voltage from a second voltage source, the first voltage being different from the second voltage.