GaN-Si Cascode Transistor Flip-Chip Bonding Parasitic Inductance
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Solution Overview
Problem
Conventional wire bonding in GaN HEMT and Si MOSFET cascode transistors introduces additional parasitic inductance, increases manufacturing costs due to the need for thicker passivation layers, and requires more expensive vertical structures.
Innovation Solution
The semiconductor device employs flip-chip bonding between a GaN high electron mobility transistor and a Si metal oxide semiconductor field effect transistor, using a patterned conductive layer to connect the transistors and reduce parasitic inductance, thereby lowering costs and enhancing device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect GaN HEMT and field effect transistor, then the transistors can be electrically connected, but additional parasitic inductance is introduced that limits frequency response and worsens device characteristics
Solution Approach 1:
The patent removes the wire bonding connection between the GaN HEMT drain and field effect transistor gate, extracting the harmful parasitic inductance from the circuit. The transistors are instead connected through direct substrate contact, eliminating the intermediate connection wire that causes the harmful effect.
Solution Approach 2:
The patent merges the electrical connection function into the substrate itself by creating a conductive path through the substrate material. The substrate serves dual purposes as both mechanical support and electrical connection medium, combining structural and electrical functions to eliminate parasitic inductance.
2Reliability
If wire bonding is used to connect the transistors, then electrical connection is achieved, but the field effect transistor must use a planar structure which increases manufacturing cost
Solution Approach 1:
Instead of using a planar field effect transistor structure that requires wire bonding, the patent inverts the approach by using a vertical field effect transistor structure that can be directly connected to the GaN HEMT through the substrate. This inversion of the conventional connection approach enables cost-effective manufacturing.
3Manufacturing precision
If the passivation layer thickness is increased to avoid overlap between GaN HEMT drain and other electrodes, then electrode overlap is prevented, but manufacturing cost increases
Solution Approach 1:
The patent resolves the electrode overlap issue by changing the spatial dimension of the connection path. Instead of increasing vertical passivation layer thickness, the connection is routed through the substrate plane, allowing thin passivation layers while maintaining proper electrode spacing and alignment.
Data Source
AI summary
A semiconductor device comprises a substrate, a patterned conductive layer, a first transistor structure and a second transistor structure. The patterned conductive layer is formed on the substrate. The first transistor structure includes a first source, a first gate and a first drain and is electrically connected to the patterned conductive layer by flip-chip bonding. The second transistor structure includes a second source, a second gate and a second drain and is electrically connected to the patterned conductive layer by flip-chip bonding. The first gate is electrically connected to the second source through the patterned conductive layer, and the first source is electrically connected to the second drain through the patterned conductive layer.