Cascoded CMOS Output Driver With Capacitive Vds Stress Reduction
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Solution Overview
Problem
Existing high voltage IO interfaces using low voltage devices face reliability issues due to over-voltage stress, leading to degradation like Hot Carrier Injection (HCI), Bias Temperature Instability (BTI), and Time-Dependent Dielectric Breakdown (TDDB), which are not adequately addressed by prior pulse-based techniques that complicate pulse width and synchronization across different PVT corners.
Innovation Solution
A cascoded output driver circuit design utilizing PMOS and NMOS transistors with capacitive coupling between gates to reduce Vds stress, self-synchronized with switching signals, and incorporating buffers and resistors to introduce delays and reduce noise, ensuring minimal Vds stress across devices while being self-PVT compensated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If cascode technique is used to design 2×VDD voltage level IO buffer, then high voltage IO interface is achieved, but Vds stress across cascoded devices becomes very high during transition
Solution Approach 1:
The patent applies preliminary action by pre-charging the gate of the cascoded device through a dedicated charge path before the main switching event. This ensures the gate is already at the required voltage level when the switching occurs, preventing excessive Vds stress during the transition. The charge pump circuit activates before the output switching to prepare the cascoded device gate voltage in advance.
Solution Approach 2:
The patent introduces an intermediary charge pump circuit that mediates between the power supply and the cascoded device gate. This intermediary circuit provides the necessary gate voltage through a controlled charge path, acting as a buffer that prevents direct high voltage stress on the cascoded device during switching transitions.
2Object-affected harmful factors
If pulse based approach is used to reduce Vds stress, then some stress reduction is achieved, but pulse width and synchronization becomes complex across different PVT corners
Solution Approach 1:
The patent implements self-service by making the charge pump circuit automatically activated by the switching signals themselves. The charge pump is triggered by the same PD0 and ND0 signals that control the output switches, creating a self-synchronized system that automatically adapts to process, voltage, and temperature variations without requiring external pulse width control or complex synchronization logic.
Solution Approach 2:
The patent applies periodic action through the charge pump circuit that operates in periodic synchronization with the switching signals. The charge pump activates during each switching cycle to recharge the gate capacitance, providing periodic stress relief that maintains low Vds stress across all operating conditions without requiring complex pulse width modulation.
3Length of moving object
If low voltage devices are used for high voltage IO interfaces, then device scaling is achieved, but over-voltage stress results in reliability degradation
Solution Approach 1:
The patent applies preliminary action by pre-charging the gate of the cascoded device through a dedicated charge path before the main switching event. This ensures the gate is already at the required voltage level when the switching occurs, preventing excessive Vds stress during the transition. The charge pump circuit activates before the output switching to prepare the cascoded device gate voltage in advance.
Solution Approach 2:
The patent implements beforehand cushioning by providing a dedicated charge pump circuit that continuously maintains the gate voltage of cascoded devices at safe levels. This cushioning effect prevents voltage spikes and excessive stress from reaching the devices during switching transitions, protecting against HCI, BTI, and TDDB degradation mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively minimizes Vds stress across cascoded devices, reduces switching noise, and lowers power consumption and chip area requirements, resulting in improved reliability and extended operating life.
Implementation Method 1
a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor
Implementation Method 2
A buffer is interposed between the first switching signal and the gate of the first transistor to introduce a delay, and a buffer is interposed between the second switching signal and the gate of the fourth transistor to introduce a delay
Data Source
AI summary
An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.