Cascoded ESD Clamp Circuit for Mixed-Voltage I/O Protection

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing ESD protection circuits in semiconductor devices are inadequate for high voltage applications, particularly in mixed-voltage I/O interfaces, leading to increased resistance and difficulty in activating ESD clamp circuits, which can result in damage from ESD events.

Innovation Solution

Implementing ESD clamp circuits with LDMOS transistors and a cascoded inverter structure, including a voltage divider and cascoded transistors, to provide efficient ESD discharge paths and protect against high voltage fluctuations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If existing ESD protection circuits are used in high voltage applications, then the device can operate in mixed-voltage I/O interfaces, but the resistance increases and activation of ESD clamp circuits becomes difficult

Engineering Contradiction:

Improvemixed-voltage I/O interface capabilityVSAvoidESD clamp circuit activation

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The ESD protection circuit is segmented into multiple components: a voltage divider circuit that divides the high voltage, a clamp circuit that activates at lower voltages, and an inverter circuit that provides signal inversion. This segmentation allows each component to operate within its optimal voltage range, enabling reliable ESD protection in mixed-voltage environments.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The voltage divider circuit acts as an intermediary between the high voltage node and the clamp circuit. It transforms the high voltage into a lower voltage that can reliably trigger the clamp circuit, thereby mediating the activation problem in high voltage applications.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If ESD clamp circuits are activated to protect against ESD events, then protection is provided, but power loss increases

Engineering Contradiction:

ImproveESD protectionVSAvoidpower loss

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The ESD clamp circuit is designed to be dynamic, activating only when ESD events are detected through the voltage divider and inverter circuits. During normal operation, the clamp remains inactive to minimize power loss, but quickly activates when needed to provide protection.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The circuit performs preliminary detection of ESD events through the voltage divider and inverter stages before activating the clamp. This preliminary anti-action allows the system to prepare for and respond to ESD threats only when necessary, avoiding unnecessary activation and associated power loss.

Inventive Principle:

Principle #9Preliminary anti-action

Data Source

PatentUS12451687B2Semiconductor device and electrostatic discharge clamp circuit

Publication Date: 2025.10.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit to discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.