Cascoded GaN FET Layout for Gain and Voltage Handling

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current field effect transistors (FETs) face challenges in achieving high gain, high operating frequency, and high bandwidth while efficiently handling voltage in radio frequency applications, particularly in power amplifiers for 5G telecommunications, due to limitations in die space and increased routing parasitics.

Innovation Solution

The design incorporates cascoded contact fingers with a first gate contact finger of shorter channel length for higher gain and bandwidth, and a second gate contact finger with longer channel length and field plates to handle high voltage, integrated within a wide bandgap transistor structure, such as Gallium Nitride (GaN), to optimize performance in power amplifiers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single gate contact finger is used, then the device complexity is low, but the gain and bandwidth are limited

Engineering Contradiction:
Improvecontact configurationVSAvoidgain and bandwidth
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The gate contact structure is segmented into multiple fingers (first gate contact finger and second gate contact finger) with different channel lengths. This segmentation allows each finger to contribute differently to the overall transistor performance, enabling higher gain and bandwidth while managing voltage handling requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the gate contact structure are assigned different properties: the first gate contact finger has a shorter channel length optimized for high-frequency operation and gain, while the second gate contact finger has a longer channel length optimized for voltage handling. This local differentiation resolves the contradiction between performance and complexity.

Inventive Principle:
Principle #3Local quality

2Productivity

If a shorter channel length is used, then the gain and operating frequency increase, but the voltage handling capability decreases

Engineering Contradiction:
Improvegain and operating frequencyVSAvoidvoltage handling capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The gate is divided into segments with different channel lengths. The first gate contact finger uses shorter channel length to achieve high gain and operating frequency, while the second gate contact finger uses longer channel length to ensure adequate voltage handling capability. Both segments work together in a cascoded configuration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The channel length parameter is varied across different gate contact fingers rather than using a uniform length. This parameter change allows optimization of each finger for its specific function (high-frequency operation vs. voltage handling) while maintaining overall transistor reliability and performance.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If more gate contact fingers are added, then the gain and bandwidth improve, but the die size increases

Engineering Contradiction:
Improvegain and bandwidthVSAvoiddie size
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The multiple gate contact fingers are arranged in a cascoded configuration that utilizes vertical stacking and layered routing rather than simple lateral expansion. This dimensional approach allows multiple fingers to be integrated within a compact die area while maintaining their individual contributions to gain and bandwidth.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Area of stationary object

If the transistor area is reduced, then the die size decreases, but the routing parasitics increase

Engineering Contradiction:
Improvetransistor areaVSAvoidrouting parasitics
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The cascoded finger configuration with vertical stacking and multi-layer routing reduces the lateral footprint while maintaining adequate routing paths. This dimensional reorganization allows compact integration without proportionally increasing routing parasitics, as the routing can be distributed across multiple layers and optimized for each finger's location.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240282831A1Field effect transistor
Publication Date: 2024.08.22 SKYWORKS SOLUTIONS INC
  • US20240282831A1 patent drawing
  • US20240282831A1 patent drawing
  • US20240282831A1 patent drawing

AI summary

A power amplifier can include at least one field effect transistor integrated within an associated transistor area. The transistor has transistor contacts with a contact configuration of cascoded contact fingers. The contact fingers include a source contact finger, a drain contact finger, a first gate contact finger provided between the source contact finger and the drain contact finger, and a second gate contact finger provided between the source contact finger and the drain contact finger.