Cascoded Level Shifter Circuit for Bipolar Clock Generation
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Solution Overview
Problem
Current level shifter circuits fail to effectively generate bipolar clock signals necessary for properly turning on and off transistors in chopper amplifier circuits, leading to signal leakage and distortion, especially at high temperatures, due to their unipolar nature and inability to match voltage levels between clock and input signals.
Innovation Solution
A level shifter circuit is designed to generate bipolar clock signals by using multiple transistor pairs and a clock generation circuit, allowing the clock signals to oscillate between different voltage levels, ensuring effective turn-on and turn-off of transistors, thereby reducing signal leakage and distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional unipolar level shifter circuit is used, then the circuit structure is simple, but the circuit cannot generate bipolar clock signals leading to signal leakage and distortion
Solution Approach 1:
The level shifter circuit is divided into multiple independent transistor pairs (first transistor pair, second transistor pair, third transistor pair, fourth transistor pair), each responsible for generating specific clock signals. This segmentation allows each pair to be optimized for bipolar signal generation while maintaining overall circuit functionality and reducing signal leakage.
Solution Approach 2:
The transistor pairs are cascoded and nested within each other, with the first and second transistor pairs coupled to the third and fourth transistor pairs respectively. This nested configuration enables the circuit to generate bipolar clock signals that swing both above and below the input signal voltage level, ensuring proper transistor switching without signal leakage.
2Reliability
If a unipolar clock signal is used, then the voltage level matching is simple, but the transistors cannot be properly turned on and off leading to distortion
Solution Approach 1:
The level shifter circuit dynamically generates bipolar clock signals that adapt to different voltage levels and temperature conditions. The clock signals swing both above and below the input signal voltage level, allowing the transistors to be properly turned on and off across varying temperature conditions, thereby maintaining reliable switching operation.
Solution Approach 2:
The circuit changes the voltage parameters of the clock signals to create bipolar swings. The clock generation circuit produces signals that oscillate between voltage levels higher and lower than the input signal, enabling proper transistor switching thresholds to be met across different operating conditions including high temperatures.
3Reliability
If the clock signal voltage level does not match the input signal level, then the circuit operation is simple, but signal leakage occurs especially at high temperatures
Solution Approach 1:
The level shifter circuit is divided into multiple independent transistor pairs (first transistor pair, second transistor pair, third transistor pair, fourth transistor pair), each responsible for generating specific clock signals. This segmentation allows each pair to be optimized for bipolar signal generation while maintaining overall circuit functionality and reducing signal leakage.
Solution Approach 2:
The clock generation circuit acts as an intermediary that transforms the input clock signal into bipolar clock signals with appropriate voltage levels. This intermediary circuit ensures that the generated clock signals properly match the input signal voltage levels, preventing signal leakage by ensuring correct voltage level alignment between clock and input signals.
Data Source
AI summary
In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.