Cascoded MOS ESD Protection Voltage Tolerance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Diode-isolated cascoded MOS electrostatic discharge protection devices are limited by the voltage tolerance of the gate-drain region of MOS transistors, which conflicts with the demand for high voltage devices, as drain voltage applications can exceed reliability limits due to large signal swings, stressing the drain-to-gate and drain-to-source regions.
Innovation Solution
Adding one or more MOS transistors in series with the original transistor allows biasing the gate of the additional transistor to turn it on, dividing the voltage and reducing excessive levels in the drain-gate region, while merging contact regions and increasing substrate resistivity to achieve a compromise between trigger and holding voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single MOS transistor is used in diode-isolated protection circuits, then the circuit structure is simple, but the voltage tolerance of the gate-drain region is exceeded under high voltage conditions
Solution Approach 1:
The patent divides the single MOS transistor into multiple series-connected MOS transistors (first MOS transistor and second MOS transistor). This segmentation distributes the voltage stress across multiple gate-drain regions, preventing any single region from exceeding its voltage tolerance while maintaining ESD protection functionality.
2Reliability
If MOS transistors are added in series to increase voltage tolerance, then the voltage tolerance is improved, but the device complexity increases
Solution Approach 1:
The patent merges the contact regions of the first MOS transistor and second MOS transistor to form a shared contact structure. This merging reduces the overall device footprint and simplifies the circuit layout, partially offsetting the complexity increase from adding series transistors while maintaining the voltage tolerance improvement.
3Reliability
If the spacing between components is reduced to optimize substrate resistivity, then the substrate resistivity optimization is achieved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies different spacing optimizations to different regions of the device. The contact regions are merged to minimize spacing and optimize substrate resistivity, while other regions maintain standard spacing to accommodate manufacturing tolerances. This localized quality adjustment achieves resistivity optimization without uniformly increasing precision requirements across the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the voltage tolerance of diode-isolated protection circuits, allowing for robust ESD protection at high voltages by reducing the spacing between components and optimizing substrate resistivity, thereby improving the reliability of ESD protection without relying on efficient npn devices.
Implementation Method 1
Adding one or more MOS transistors in series with the original transistor allows biasing the gate of the additional transistor to turn it on, dividing the voltage and reducing excessive levels in the drain-gate region
Implementation Method 2
diode-isolated cascoded MOS electrostatic discharge protection devices
Implementation Method 3
a first diode with its cathode connected to the power (VDD) terminal for positive ESD stress and its anode connected to the I/O pad to be protected
Implementation Method 4
relies on the mode of a parasitic bipolar transistor (the source acts as the emitter, the drain as the collector, and the bulk semiconductor as the base) during an ESD event to provide a low impedance current path to ground
Data Source
AI summary
A circuit for protecting against electrostatic discharge events has a semiconductor substrate (200) of first conductivity embedding a first diode in a well (260) of opposite second conductivity, the diode's anode (111) tied to an I/O pin-to-be-protected (101) at a first voltage, and the first diode's cathode (112) connected to the first drain (123) of a first MOS transistor in the substrate. The first MOS transistor's first gate (122) is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain (670) merged with the first source of the first MOS transistor, and its second source (131), together with its second gate (132), tied to ground potential (140).