Cascoded III-Nitride Half Bridge for Safe Power-Up

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Solution Overview

Problem

High power and high performance circuit applications using III-Nitride HEMTs face issues due to their normally ON nature, which can lead to potential damage to the load and circuit if the gate is not properly biased before power application, and integrating multiple III-Nitride HEMTs in conventional power conversion circuits is challenging.

Innovation Solution

A monolithically integrated III-Nitride half bridge circuit is developed, incorporating a depletion mode III-Nitride FET cascaded with an enhancement mode group IV MOSFET to create a normally OFF composite cascoded device, and an optional DC enable switch is used in the conduction path of the high side III-Nitride HEMT to prevent shorting across supply rails.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If a depletion mode III-Nitride HEMT is used for high power and high voltage operation, then high efficiency and high-voltage operation are achieved, but the normally ON nature can cause damage to the load and circuit if the gate is not properly biased before power application

Engineering Contradiction:

Improvehigh power and high voltage operationVSAvoidcircuit safety during power up

Core Design Contradiction:

PowerVSReliability

Solution Approach 1:

The patent applies preliminary action by implementing an enhancement mode FET (E-mode FET) that activates before the depletion mode III-Nitride HEMT during power-up. The E-mode FET is biased to turn on first, establishing a safe conduction path before the D-mode HEMT is activated. This preliminary activation prevents the D-mode device from causing short circuits or damaging the load during the critical power-up phase, while still allowing the high power capability of the III-Nitride device to be utilized once properly biased.

Inventive Principle:

Principle #10Preliminary action

2Power

If multiple III-Nitride HEMTs are integrated in conventional power conversion circuits, then high efficiency is achieved, but integration is challenging

Engineering Contradiction:

Improvehigh efficiencyVSAvoidintegration complexity

Core Design Contradiction:

PowerVSDevice complexity

Solution Approach 1:

The patent merges two different FET technologies (enhancement mode FET and depletion mode III-Nitride HEMT) into a single integrated circuit structure. The E-mode and D-mode devices are fabricated on the same substrate with shared components such as the drift region, contact structures, and interconnect layers. This merging approach enables multiple high-efficiency III-Nitride devices to be integrated in conventional power conversion circuits while reducing packaging complexity and improving thermal management.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration ensures safe power up by maintaining the high side III-Nitride FET in a high resistive state until the gate is properly biased, preventing short circuits and allowing for efficient monolithic integration of III-Nitride devices, reducing the risk of damage and simplifying packaging.

Implementation Method 1

III-Nitride and other group III-V HEMTs operate using polarization fields to generate a two-dimensional electron gas (2DEG) allowing for high current densities with low resistive losses

Methodology Applied

Scientific EffectPolarization fields:

Implementation Method 2

polarization fields to generate a two-dimensional electron gas (2DEG) allowing for high current densities with low resistive losses

Methodology Applied

Scientific EffectTwo-dimensional electron gas (2DEG):

Implementation Method 3

The field-effect transistor is a transistor that uses an electric field to control the conductivity of the channel

Methodology Applied

Scientific EffectElectric field control: Electric Field

Implementation Method 4

form a normally OFF cascoded composite device including a D-mode III-Nitride HEMT cascoded with a low voltage (LV) enhancement mode (E-mode) silicon (Si) metal-oxide-semiconductor FET (MOSFET)

Methodology Applied

Scientific EffectCascoded configuration:

Data Source

PatentUS9406674B2Integrated III-nitride D-mode HFET with cascoded pair half bridge

Publication Date: 2016.08.02 INFINEON TECHNOLOGIES AMERICAS CORP

AI summary

There are disclosed herein various implementations of a group III-V power conversion circuit including a monolithically integrated half bridge having a depletion mode III-Nitride field-effect transistor (FET), and a normally OFF composite cascoded switch including a depletion mode III-Nitride FET and an enhancement mode group IV FET. In one exemplary implementation, the monolithically integrated half bridge includes a high side depletion mode III-Nitride FET having an enable switch coupled in the conduction path of the high side depletion mode III-Nitride FET.