Cascoded Output Driver Protection for High-Voltage PAD Faults
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Solution Overview
Problem
Integrated circuits (ICs) face damage from high-voltage faults due to gate-oxide stress, electromigration, and ground bounce, particularly in interface circuits with mismatched voltage levels, leading to performance degradation and component damage.
Innovation Solution
A protection circuit using cascoded PMOS and NMOS transistors with controlled safe signals to manage voltage differences, preventing excessive stress and current flow during high-voltage conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If interface circuits work in lower voltage technology (e.g., 3.3V) while coupled to external high-voltage circuits (e.g., 5V), then device power consumption is reduced and integration density is improved, but gate-oxide stress and device damage occur due to voltage mismatch
Solution Approach 1:
The patent introduces protection circuits as intermediary components between the low-voltage interface circuit and high-voltage external circuit. These protection circuits include voltage clamping devices and current limiting devices that mediate the voltage mismatch, allowing the interface circuit to operate at lower voltage while being protected from high-voltage damage
Solution Approach 2:
The patent segments the interface circuit into protected internal components operating at low voltage and protection circuits that handle high-voltage interfacing. This segmentation allows different parts of the system to operate at appropriate voltage levels, with the protection circuit acting as a buffer zone between voltage domains
2Adaptability or versatility
If output stage voltage is higher than interface circuit voltage (e.g., 5V vs 3.3V), then external circuit compatibility is improved, but huge current flow from output stage to buffer circuit causes electromigration and component damage
Solution Approach 1:
The patent introduces current limiting devices and protection circuits as intermediaries between the high-voltage output stage and low-voltage buffer circuit. These devices control and limit the current flow, preventing electromigration while maintaining voltage level compatibility between different circuit blocks
Solution Approach 2:
The patent changes the electrical parameters (current limiting, voltage clamping) of the protection circuits to match the voltage and current characteristics of both the high-voltage output stage and low-voltage buffer circuit, enabling safe operation across voltage domains
3Power
If huge current flows from output stage to ground, then high-voltage drive capability is achieved, but ground bounce occurs affecting switching performance and causing unstable operation
Solution Approach 1:
The patent introduces ground protection circuits and current limiting devices as intermediaries between the high-voltage output stage and ground. These devices manage the return current path, preventing ground bounce while maintaining high-voltage drive capability
4Reliability
If protection circuits are added to prevent high-voltage damage, then device reliability is improved, but circuit complexity and device area increase
Solution Approach 1:
The patent designs protection circuits that perform multiple functions: voltage clamping, current limiting, and ground protection. By making the protection circuits multi-functional, the patent reduces the need for separate protection devices for each function, thereby limiting the increase in circuit complexity
Data Source
AI summary
The present disclosure is directed to a high-voltage fault protection for an interface circuit. The interface circuit is transmitting data signals through an output driver to an external circuit coupled to a PAD contact. The output driver includes pull-up and pull-down drivers. The pull-up driver includes two series PMOS coupled between a voltage supply and the PAD. The pull-down driver includes two series NMOS coupled between the PAD and a ground node. A first safe signal is coupled to one PMOS. A first circuit scheme is designed to generate the first safe signal to be low-logical level voltage when the PAD voltage is lower than a threshold, while being high-logical level voltage when the PAD voltage is higher than the threshold. A second circuit scheme is designed to control one of the series NMOS to be in OFF state when the PAD voltage is higher than the threshold.