Cascoded Semiconductor Device Parasitic Reduction
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Solution Overview
Problem
Cascoded semiconductor devices using silicon and III-N semiconductor materials face reliability issues due to high leakage currents and parasitic effects when packaged separately, leading to increased costs and performance degradation.
Innovation Solution
A cascoded semiconductor device is fabricated with a III-nitride semiconductor chip mounted in a flip-chip configuration on a conductive support, where the substrate is electrically isolated from leads, and an interconnect connects the substrate to the source, allowing for biasing and reducing parasitic effects by integrating the devices in a single package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If cascoded devices are packaged separately and connected via leadframe leads, then manufacturing is easier, but parasitic capacitance and inductance increase, degrading device performance
Solution Approach 1:
The patent merges the silicon device and III-N device into a single integrated package, eliminating the need for external leadframe connections. The devices are connected through integrated interconnect structures within the package, which significantly reduces parasitic capacitance and inductance while maintaining ease of manufacture through standardized packaging processes.
Solution Approach 2:
The patent introduces an intermediary substrate structure that hosts both the silicon device and III-N device, enabling their integration within a single package. This intermediary substrate provides mechanical support and electrical interconnection, allowing the devices to be connected with minimal parasitics while simplifying the manufacturing process.
2Device complexity
If cascoded devices are packaged separately, then packaging complexity is reduced, but the number of packages increases, increasing cost
Solution Approach 1:
The patent combines multiple devices that would traditionally require separate packages into a single integrated package. This reduces the total number of packages needed, lowering material costs and assembly complexity while maintaining ease of manufacture through standardized packaging techniques.
3Power
If silicon device operates in avalanche mode, then switching capability is improved, but gate stress increases, degrading device reliability
Solution Approach 1:
The patent introduces an intermediary substrate structure that enables optimized electrical connections and heat dissipation paths. This intermediary structure helps manage the stress conditions during avalanche operation, allowing the silicon device to operate in avalanche mode for improved switching capability while mitigating gate stress through better thermal and electrical management.
Data Source
AI summary
In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support.