Cascoded Semiconductor Integration Reducing Parasitics
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Solution Overview
Problem
The existing method of manufacturing cascoded semiconductor devices, which involves separate packaging of silicon and III-N semiconductor materials, increases costs and degrades performance due to parasitic capacitance and inductance, necessitating a more cost-efficient approach to integrate these devices in a single package.
Innovation Solution
A cascoded semiconductor device and manufacturing method that integrates silicon and III-N semiconductor components in a single package, utilizing a silicon chip with a III-N cascode switch where the III-N substrate is electrically floating, and bond pads are not formed over active areas to reduce parasitics and enhance thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon and III-N semiconductor devices are packaged separately and connected via leadframe leads, then device protection and manufacturing simplicity are improved, but parasitic capacitance and inductance increase, degrading device performance
Solution Approach 1:
The patent merges previously separate silicon and III-N semiconductor devices into a single integrated package. The silicon device and III-N device are mounted on the same substrate with direct electrical connections, eliminating the need for external leadframe connections. This integration reduces parasitic elements while maintaining manufacturing feasibility through standardized packaging processes.
2Reliability
If the number of packages is increased to protect silicon and III-N devices separately, then device protection is improved, but manufacturing cost increases and device performance degrades
Solution Approach 1:
The invention combines multiple device protection functions into a single package structure. Both silicon and III-N devices are housed together with shared packaging elements, reducing the total number of packages required. This approach maintains adequate protection while lowering manufacturing costs associated with multiple discrete packages.
3Ease of manufacture
If separate packages are used for silicon and III-N devices, then manufacturing process simplicity is improved, but parasitic inductance and capacitance increase, reducing device performance
Solution Approach 1:
The patent introduces a shared substrate as an intermediary element that hosts both silicon and III-N devices. This substrate provides direct electrical interconnection between devices, serving as a low-parasitic mediator that replaces external leadframe connections. The intermediary substrate enables simplified manufacturing while minimizing harmful parasitic effects through controlled impedance design.
4Reliability
If devices are integrated in a single package, then parasitic effects are reduced and performance is improved, but manufacturing complexity increases
Solution Approach 1:
The integrated package is segmented into distinct functional regions for silicon and III-N devices, each with optimized layout and interconnection. This segmentation allows independent optimization of each device while maintaining compact integration. The modular segmentation reduces manufacturing complexity by enabling standardized assembly procedures for each segment within the unified package.
Data Source
AI summary
In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure and a second device receiving structure and a contact extension that is common to the first and second device receiving structures. The first device receiving structure includes a device receiving area and the second device receiving structure includes a drain contact area. A III-N based semiconductor chip has a drain bond pad bonded to the drain contact area and a source bond pad bonded to the contact extension and a gate bond pad bonded to an interconnect. A portion of the silicon based semiconductor chip is bonded to the support device receiving area. In accordance with another embodiment, a method for manufacturing the semiconductor component includes coupling a III-N based semiconductor chip to a portion of the support a silicon based semiconductor chip to another portion of the support.