Cascoded Semiconductor Device Parasitic Reduction
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Solution Overview
Problem
The increasing number of packages in cascoded semiconductor components leads to higher costs and performance degradation due to parasitic capacitance and inductance, making existing manufacturing methods inefficient.
Innovation Solution
A cascoded semiconductor device is designed with a silicon chip and a III-Nitride chip mounted in a flip-chip configuration, where the III-Nitride substrate is either floating or coupled to the source electrode, and both chips are packaged in a QFN or through-hole package with thermally enhanced mold compounds and ceramic materials to reduce parasitics and improve thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate packages are used for silicon device and depletion mode devices, then protection of devices is achieved, but cost increases and performance degrades due to increased parasitics
Solution Approach 1:
The patent combines multiple semiconductor devices (silicon device and III-N depletion mode device) into a single integrated package structure. The devices are mounted on a common substrate with shared packaging elements, reducing the total number of separate packages while maintaining individual device protection through dedicated mounting areas and encapsulation.
Solution Approach 2:
The patent introduces a common substrate as an intermediary platform that hosts both the silicon device and III-N depletion mode device. This substrate serves as a mediator that enables electrical interconnection between devices while providing mechanical support and thermal management, thereby reducing the need for multiple separate packages and leadframe connections.
2Reliability
If separate packages are used for silicon device and depletion mode devices, then device protection is achieved, but cost increases
Solution Approach 1:
The patent merges multiple device packages into a single integrated package structure, reducing the total component count and assembly steps. This consolidation lowers manufacturing costs by reducing materials (fewer packages, leadframes, and interconnectors) and simplifying the assembly process while maintaining individual device protection through dedicated mounting regions.
Solution Approach 2:
The common substrate serves multiple functions simultaneously: it provides mechanical support for both devices, enables electrical interconnection, facilitates thermal management, and simplifies packaging. This multi-functionality reduces the need for separate protective structures for each device, thereby lowering overall manufacturing cost while maintaining protection.
3Reliability
If multiple packages are used to connect devices, then device protection is achieved, but parasitic capacitance and inductance increase
Solution Approach 1:
The common substrate acts as an intermediary that provides low-inductance electrical interconnection between the silicon device and III-N depletion mode device. By eliminating the need for external leadframe connections between separate packages, the substrate minimizes parasitic inductance and capacitance while still providing adequate protection through its encapsulation structure.
Solution Approach 2:
The patent transitions from a three-dimensional arrangement of separate packages connected by leadframes to a planar integration on a common substrate. This dimensional change reduces the physical distance between devices and interconnection paths, thereby minimizing parasitic effects while maintaining device protection through the substrate's encapsulation.
Data Source
AI summary
In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support.