Cascoded Silicon and GaN Semiconductor Component
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Solution Overview
Problem
Cascoded semiconductor devices using silicon and III-N semiconductor materials face reliability issues due to high leakage currents and parasitic capacitance/inductance, increasing costs and degrading performance with multiple packages.
Innovation Solution
A cascoded semiconductor device configuration where silicon and III-N semiconductor chips are integrated on a single support structure, eliminating the need for separate packages by using a flip-chip configuration and bonding wires, reducing parasitic effects and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If separate packages are used for silicon device and depletion mode device, then manufacturing and packaging are simplified, but parasitic capacitance and inductance increase, degrading device performance
Solution Approach 1:
The patent merges the silicon device and III-N depletion mode device into a single integrated package structure. The support structure integrates both devices with their interconnections, eliminating the need for separate packages and leadframe leads. This integration reduces parasitic capacitance and inductance while maintaining manufacturing feasibility through a unified packaging approach.
2Ease of manufacture
If separate packages are used for silicon device and depletion mode device, then manufacturing process is simplified, but manufacturing cost increases due to increased number of packages
Solution Approach 1:
The patent combines multiple devices into a single integrated package, reducing the total number of packages required. This integration decreases manufacturing costs by eliminating redundant packaging materials and reducing assembly steps, while the unified support structure maintains ease of manufacture through standardized integration processes.
3Power
If silicon device operates in avalanche mode to handle high leakage currents, then device can function under high drain bias, but gate stress increases and reliability degrades
Solution Approach 1:
The patent utilizes the high leakage current characteristic of the III-N depletion mode device operating in avalanche mode not as a harmful effect to be avoided, but as a beneficial feature for achieving normally-off operation. The integrated structure manages the gate stress conditions by designing the cascode configuration to tolerate and utilize these high-stress conditions for achieving the desired device functionality.
Data Source
AI summary
In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead, a second lead, and a third lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.