Cascoded Power Switch Gate Control for Cross-Conduction Prevention
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Solution Overview
Problem
Existing DC-DC converters face challenges in managing inductive voltage drops and preventing cross conductance between high-side and low-side power switches, which can lead to device damage due to excessive voltage ratings.
Innovation Solution
Implementing cascoded power switches with driver circuits that include voltage monitor circuits to control the gate voltages of high-side and low-side switches, using cascoded PMOS and NMOS transistors, and employing split gate drive techniques to manage inductive parasitics and prevent cross conductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cascoded power switches are implemented to manage inductive voltage drops and prevent cross conductance, then device reliability is improved, but circuit complexity increases
Solution Approach 1:
The power switch is segmented into multiple cascoded transistors (first, second, third transistors in series) with intermediate nodes, dividing the voltage stress and control functions across multiple devices. This segmentation allows better management of inductive voltage drops and prevention of cross conductance while maintaining reliability.
Solution Approach 2:
Intermediate nodes are introduced between the cascoded transistors to serve as voltage monitoring points. These intermediary nodes enable the driver circuit to detect voltage conditions and control gate voltages appropriately, resolving the contradiction by providing a mechanism to manage complex voltage conditions without requiring overly complex control logic.
2Reliability
If voltage monitor circuits are used to control gate voltages of cascoded switches, then cross conductance prevention is improved, but device complexity increases
Solution Approach 1:
Voltage monitor circuits continuously monitor the voltage at intermediate nodes and provide feedback to the driver circuit. This feedback mechanism enables real-time adjustment of gate voltages to prevent cross conductance between high-side and low-side switches, improving reliability through closed-loop control.
Solution Approach 2:
The voltage monitor circuits automatically detect voltage conditions at intermediate nodes and trigger appropriate control actions without external intervention. The system self-regulates by monitoring its own state and adjusting gate voltages accordingly, preventing cross conductance through autonomous operation.
3Reliability
If split gate drive techniques are employed to manage inductive parasitics, then inductive voltage drop management is improved, but control circuit complexity increases
Solution Approach 1:
The driver circuit is designed to apply gate voltages in a predetermined sequence and with specific timing relationships. By preliminarily establishing the correct gate voltage sequence before switching events, the circuit proactively manages inductive voltage drops rather than reacting to them, reducing the need for complex real-time control.
Solution Approach 2:
The gate drive signals are applied periodically with specific duty cycles and timing patterns that synchronize with the switching frequency. This periodic action allows the driver circuit to manage inductive parasitics through rhythmic, predictable gate voltage application, simplifying control compared to aperiodic or continuously adjusted schemes.
Data Source
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AI summary
A cascoded power switch includes a high-side (HS) switch between an output node and a first voltage supply terminal and a low-side switch. The HS switch includes a first, second, and third transistor in series between the first voltage supply terminal and the output node, and a fourth, fifth, and sixth transistor in series between the first voltage supply terminal and the output node. The first and fourth transistors are in parallel, the second and fifth transistors are in parallel, and the third and sixth transistors are in parallel. A HS driver circuit begins turning on the first transistor in response to assertion of a first control signal and delays turning on the fourth transistor until both the first and second controls signal are asserted. A voltage monitoring circuit includes logic which asserts the second control signal in response to a rise of an output voltage at the output node.