Catalytic Adhesive for Wafer Level Packaging

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Solution Overview

Problem

Wafer level packaging processes often require multiple steps and materials, including traditional dielectric materials, which can be inefficient and costly, particularly in forming metal traces and insulating layers.

Innovation Solution

The use of a catalytic adhesive with catalytic particles, such as palladium, iron, or silver, that reduces electroless copper from Cu++ to Cu, allowing for the formation of metal traces within trace channels on the wafer surface, reducing the need for traditional dielectric materials and processing steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional dielectric materials are used for insulating layers and metal trace formation, then effective insulation and connectivity are achieved, but processing complexity and cost increase due to multiple steps and materials

Engineering Contradiction:
Improveinsulation effectivenessVSAvoidprocessing steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple functions into a single catalytic adhesive layer that simultaneously provides dielectric insulation, metal trace formation through catalytic particles, and adhesion. This eliminates the need for separate dielectric layers and metal deposition steps, directly reducing processing complexity while maintaining insulation effectiveness through the dielectric properties of the adhesive matrix

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The catalytic adhesive layer serves multiple functions: it acts as a dielectric insulating layer, provides catalytic sites for electroless copper plating to form metal traces, and maintains adhesion between layers. This multi-functionality reduces the number of processing steps and materials required while ensuring both insulation and connectivity are achieved

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If traditional dielectric materials and multiple processing steps are used, then reliable insulation and metal trace formation are achieved, but manufacturing cost increases

Engineering Contradiction:
Improveconnectivity reliabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

By merging the dielectric layer and metal trace formation function into a single catalytic adhesive layer, the patent eliminates multiple processing steps including separate dielectric deposition, patterning, and metal deposition steps. This consolidation reduces manufacturing complexity and cost while maintaining connectivity reliability through the integrated catalytic plating process

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The catalytic particles in the adhesive layer enable self-catalyzed electroless copper plating, where the copper deposition occurs automatically in the presence of the catalytic particles without requiring additional external catalyst application steps. This self-service mechanism simplifies the manufacturing process and reduces costs while ensuring reliable metal trace formation

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the wafer level packaging process by directly forming metal traces on the wafer surface, reducing processing complexity and potentially lowering costs while maintaining effective insulation and connectivity.

Implementation Method 1

A catalytic adhesive is dielectric material that will adhere to a wafer surface and that includes catalytic particles that will reduce electroless copper (Cu) from Cu++ to Cu

Methodology Applied
Scientific EffectCatalysis: Catalysis

Implementation Method 2

The catalytic particles are composed of at least one of: palladium (Pd) particles, iron (Fe) particles, and silver (Ag) particles

Methodology Applied
Scientific EffectElectroless copper reduction: Redox Reactions

Data Source

PatentUS10573610B2Method for wafer level packaging
Publication Date: 2020.02.25 CATLAM LLC
  • US10573610B2 patent drawing
  • US10573610B2 patent drawing
  • US10573610B2 patent drawing

AI summary

Wafer level packaging includes a first layer of a catalytic adhesive on a wafer surface. The catalytic adhesive includes catalytic particles that will reduce electroless copper (Cu) from Cu++ to Cu. Metal traces are formed in trace channels within the first layer of catalytic adhesive. The trace channels extend below a surface of the first layer of the catalytic material. The trace metals traces are also in contact with integrated circuit pads on the surface of the wafer.