Cavity Chip Package with Conformal Metal Layer
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Solution Overview
Problem
The increasing density and decreasing size of integrated circuit chips pose challenges in forming connection paths and heat dissipation, affecting chip performance due to high heat generation and complex input/output connections.
Innovation Solution
A chip package design that includes a substrate with a cavity, a conformally covering metal layer, and a protective layer, where the chip is bonded using a soft insulating layer that is hardened, allowing for effective heat dissipation and relaxed distribution of conducting structures like solder balls on a protective layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the chip size is reduced and device density is increased to save wafer area, then manufacturing cost is reduced and chip performance is improved, but heat generation increases and connection path formation becomes more difficult
Solution Approach 1:
The patent introduces a cavity structure extending downward from the substrate surface, creating a vertical dimension for heat dissipation. The metal layer is positioned within this cavity beneath the chip, utilizing the subsurface volume rather than expanding the chip footprint horizontally. This dimensional transition enables effective thermal management and connection path formation without increasing the chip area, thus resolving the contradiction between high-density integration and heat dissipation.
2Productivity
If the chip size is reduced and device density is increased, then manufacturing cost is reduced, but the amount and density of input/output connections increase making connection path formation difficult
Solution Approach 1:
The cavity structure provides additional vertical space for routing connection paths. Conductive structures can be formed within the cavity volume and along the cavity sidewalls, distributing I/O connections in three dimensions rather than constrained to a two-dimensional surface. This dimensional expansion simplifies the formation of high-density connection paths by providing more routing options and reducing congestion on the chip surface.
3Temperature
If a metal layer is added to cover the chip for thermal management and grounding, then heat dissipation is improved, but the device structure becomes more complex
Solution Approach 1:
The metal layer within the cavity serves multiple functions simultaneously: it acts as a heat sink for thermal management, provides grounding connections for electrical stability, and can serve as an electromagnetic shielding layer. By consolidating these multiple functions into a single structural element positioned within the cavity, the patent achieves effective thermal management without proportionally increasing structural complexity.
Solution Approach 2:
The metal layer is positioned in the vertical dimension within the cavity beneath the chip, utilizing the subsurface volume. This spatial arrangement allows thermal management functionality to be added without occupying horizontal chip area or significantly increasing the overall package footprint, thereby minimizing the impact on structural complexity while achieving effective heat dissipation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances heat dissipation, simplifies the formation of high-density connections, and reduces the chip package size by utilizing the metal layer for both thermal management and grounding, while allowing for flexible chip placement and easy packaging.
Implementation Method 1
a metal layer overlying the substrate and conformally covering a sidewall and also a bottom portion of the cavity
Implementation Method 2
bonding at least one chip overlying the soft insulating layer, hardening the soft insulating layer to form an insulating layer
Data Source
AI summary
An embodiment provides a chip package including a substrate, a cavity extending downward from an upper surface of the substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and the protective layer covering the chip.