Semiconductor Package Cavity Structure for Spacer-Free Chip Stacking
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Solution Overview
Problem
The size of semiconductor packages is limited due to the area occupied by semiconductor elements, particularly capacitors, which restricts the packaging of multiple chips.
Innovation Solution
A semiconductor package design that includes a package substrate with a cavity for semiconductor elements to protrude, supporting multiple stacked semiconductor chips, reducing the need for a conventional spacer chip and minimizing package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If semiconductor elements (capacitors) are mounted on the package substrate to reduce power noise, then power noise reduction is improved, but package size increases due to occupied area
Solution Approach 1:
The patent transitions semiconductor elements from a planar mounting configuration to a three-dimensional vertical arrangement by forming cavities in the package substrate. Capacitors are mounted within these cavities and extend vertically, allowing power noise reduction functionality to be achieved without increasing the horizontal package footprint.
Solution Approach 2:
The patent embeds semiconductor elements (capacitors) within cavities formed in the package substrate structure. This nesting approach allows the capacitors to be integrated into the substrate volume rather than occupying surface area, enabling multiple components to coexist in a compact arrangement where smaller elements are positioned within the structural volume of the substrate.
2Strength
If a conventional spacer chip is used to support stacked memory chips, then structural support is improved, but package size and cost increase
Solution Approach 1:
The patent removes the conventional spacer chip component from the package structure and replaces it with semiconductor elements (capacitors) that are mounted within cavities in the package substrate. This extraction eliminates the need for a separate spacer chip while maintaining the structural support function through the vertical arrangement of capacitors and memory chips.
Solution Approach 2:
The patent makes the semiconductor elements (capacitors) serve dual functions: they provide power noise reduction functionality and simultaneously serve as structural spacers to support the stacked memory chips. This multi-functionality eliminates the need for dedicated spacer chips, reducing both package size and component count.
3Reliability
If semiconductor elements are mounted on the package substrate surface, then electrical connectivity is improved, but mounting area increases
Solution Approach 1:
The patent transitions electrical connectivity from a two-dimensional surface mounting arrangement to a three-dimensional configuration where semiconductor elements are positioned within cavities and extend vertically. This allows electrical connections to be established through vertical pathways via bonding pads and bonding wires, reducing the horizontal mounting area required.
Data Source
AI summary
A semiconductor package may include: a package substrate including a first region and a second region adjacent to the first region, the package substrate further including a cavity that is recessed from an upper surface of the package substrate in the second region; a first semiconductor chip on the upper surface of the package substrate, wherein the first semiconductor chip is on the first region of the package substrate; at least one semiconductor element in the cavity of the package substrate, the at least one semiconductor element protruding above the upper surface of the package substrate; second semiconductor chips sequentially stacked on the at least one semiconductor element and overlapping with the first semiconductor chip, wherein the second semiconductor chips are connected to each other and the first semiconductor chip by adhesive films; and a molding member on the second semiconductor chips and the package substrate.