Cavity-Gate FET Layout for Low On-Resistance Across Mixed Sizes
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Solution Overview
Problem
Existing technologies face challenges in mounting field effect transistors with different planar sizes together on the same semiconductor substrate, which hinders the reduction of on-resistance and the miniaturization of wireless communication devices.
Innovation Solution
A semiconductor device is developed, featuring a first and a second field effect transistor with different planar sizes, each incorporating a cavity part in the insulating layer between the main electrodes, and a gate electrode with a head part wider than its body part. The method of production involves forming insulating films, creating openings, and etching to form cavity parts of varying widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If field effect transistors with different planar sizes are mounted on the same semiconductor substrate, then the size of wireless communication device can be reduced, but it has been difficult to reduce the on-resistance of each field effect transistor
Solution Approach 1:
The patent applies local quality by providing cavity parts with different widths in the insulating layer for different field effect transistors. Specifically, the first field effect transistor has a first cavity part with a first width, while the second field effect transistor has a second cavity part with a second width different from the first. This localized differentiation allows each transistor to be optimized for its specific function (switch or power amplifier) while maintaining low on-resistance for both devices on the same substrate.
2Reliability
If the separation distance between main electrodes is shortened to reduce on-resistance, then on-resistance decreases, but device withstand voltage decreases
Solution Approach 1:
The patent resolves this contradiction by providing different cavity part widths for different transistor types. The first field effect transistor (switch) has a smaller cavity width allowing shorter electrode separation for low on-resistance, while the second field effect transistor (power amplifier) has a larger cavity width providing higher withstand voltage capability. This local differentiation enables both transistors to operate at their optimal performance points.
3Strength
If the separation distance between main electrodes is increased to increase device withstand voltage, then withstand voltage increases, but on-resistance increases
Solution Approach 1:
The patent applies local quality by differentiating the cavity part dimensions for different transistor functions. The second field effect transistor designed for high voltage operation has a larger cavity width that provides adequate voltage withstand capability, while the first transistor optimized for low resistance has a smaller cavity width. This allows each device to achieve its performance targets without compromise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the reduction of on-resistance for both field effect transistors, improving high-frequency characteristics and allowing for the miniaturization of wireless communication devices by effectively mounting transistors of different sizes on a single substrate.
Implementation Method 1
since it is possible to reduce a parasitic capacitance (Cgs) added between the gate electrode and one main electrode (source electrode) and a parasitic capacitance (Cgd) added between the gate electrode and the other main electrode (drain electrode), it is possible to reduce the on-resistance of the field effect transistor
Data Source
AI summary
The on-resistance of each of field effect transistors having different planar sizes is reduced. A semiconductor device includes first and second field effect transistors mounted on a semiconductor substrate and an insulating layer provided on a main surface of the semiconductor substrate. Here, each of the first and second field effect transistors includes a pair of main electrodes which are separated from each other and provided on the main surface of the semiconductor substrate, a cavity part which is provided in the insulating layer between the pair of main electrodes, and a gate electrode which has a head part positioned on the insulating layer and a body part that penetrates the insulating layer from the head part and protrudes toward the cavity part and in which the head part is wider than the body part. Here, the width of the cavity part of the second field effect transistor is different from the width of the cavity part of the first field effect transistor.