Cavity-Based Monolithic Inductor for High Q Factor ICs
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Solution Overview
Problem
Conventional monolithic inductors in IC devices have low Q factors and self-resonant frequencies due to conductor losses and parasitic substrate capacitances, limiting their performance and making them unsuitable for compact and reliable signal processing applications.
Innovation Solution
The formation of monolithic inductors within a cavity region with support members that intersect the inductive element, reducing parasitic losses and increasing the Q factor and self-resonant frequency by suspending the inductive element in a partially air environment while maintaining structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If monolithic inductors are formed directly on the silicon substrate, then the device size is reduced, but the Q factor and self-resonant frequency are significantly lowered due to conductor losses and parasitic substrate capacitances
Solution Approach 1:
The patent segments the substrate by forming a cavity region that removes portions of the silicon substrate beneath the inductive element. This segmentation isolates the inductor from the lossy substrate while maintaining compact integration, resolving the contradiction between small device size and high Q factor by creating a spatial separation between the inductive element and the problematic substrate regions.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional structure by forming a cavity that extends vertically through the substrate. This dimensional change allows the inductive element to be suspended above the substrate plane, reducing parasitic capacitances and conductor losses while maintaining a compact footprint, thus simultaneously achieving small device size and high Q factor.
2Reliability
If the inductive element is suspended in air to reduce parasitic losses, then the Q factor increases, but structural stability and support become problematic
Solution Approach 1:
The patent applies local quality by forming support members only at specific locations beneath the inductive element rather than providing continuous substrate support. The support members are strategically positioned to provide mechanical stability where needed while leaving the majority of the inductive element suspended in the cavity region, thus maintaining high Q factor while ensuring structural integrity.
Solution Approach 2:
The support members act as intermediaries between the suspended inductive element and the substrate. These intermediaries provide the necessary mechanical support and structural stability while minimizing the contact area between the inductor and the substrate, thereby reducing parasitic losses and maintaining high Q factor.
3Ease of manufacture
If conventional spiral inductor designs are used, then the manufacturing process is simple, but the self-resonant frequency and Q factor are limited
Solution Approach 1:
The patent maintains manufacturing simplicity by using standard semiconductor fabrication processes to form the inductive element, while introducing substrate segmentation through cavity formation. This approach preserves the ease of manufacturing conventional spiral inductors while dramatically improving self-resonant frequency and Q factor through the removed substrate portions that reduce parasitic effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly enhances the Q factor by more than 15% and self-resonant frequency by over 150% compared to conventional spiral inductors, enabling smaller and more reliable inductive elements within ICs, thus reducing device size and improving performance.
Implementation Method 1
the Q factor is primarily limited by conductor losses arising from conductor resistances, the conductive silicon substrate, and parasitic substrate capacitances
Implementation Method 2
time-varying magnetic fields can penetrate the silicon substrate and cause eddy currents as per Lenz's law, thus resulting in power loss
Data Source
AI summary
An IC device (100) includes an IC body (106) having a base layer (108) and first and second upper layers (114, 116) on the base layer. The IC body includes a cavity region (104) extending through said base and first upper layers and at least a portion of said second upper layer. In the IC device, a portion of said second upper layer in the cavity region comprises a planar inductive element (102) having first and second contacting ends (140, 142). In the IC device, at least one support member (128, 130, 132) extends at least partially into said cavity region from said IC body in at least a first direction parallel to said base layer and intersects at least a portion of said planar inductive element.