Cavity Package Output Matching Network for Parasitic Inductance Control

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Solution Overview

Problem

Conventional RF power amplifiers face performance degradation due to parasitic inductances caused by wire connections in cavity packages, leading to impedance mismatches and reduced efficiency, especially in wideband and multi-carrier signal applications.

Innovation Solution

The design incorporates a cavity package with a substrate and output lead configuration where a shunt wire and output wire are shaped to minimize self-inductance and mutual inductance by bending them to intersect at a right angle and keeping a portion of the output wire at a predetermined distance from the substrate, reducing parasitic effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional wire connections are used to connect transistor device to leads, then the device structure is simple and easy to manufacture, but parasitic inductances increase causing impedance mismatches and performance degradation

Engineering Contradiction:
Improveimpedance matching performanceVSAvoidwire configuration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The wire connections are bent into curved configurations rather than straight lines. Specifically, the first wire is bent to extend substantially perpendicular to the second wire, and both wires are positioned to extend substantially perpendicular to the longitudinal axis of the output lead. This curvature reduces the loop area and optimizes the geometric arrangement to minimize parasitic inductances while maintaining electrical connectivity.

Inventive Principle:
Principle #14Spheroidality (Curvature)

Solution Approach 2:

The wire connections are positioned in three-dimensional space above the base metal, utilizing vertical positioning to optimize inductance characteristics. The wires extend at specific heights and angles in the vertical dimension, creating a spatial arrangement that minimizes mutual inductance between the output wire and the output lead while maintaining electrical connectivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If wire length and shape are reduced to minimize parasitic inductances, then inductance decreases improving performance, but manufacturing precision requirements increase

Engineering Contradiction:
Improveinductance controlVSAvoidwire positioning precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The cavity package structure is designed with predetermined positions and dimensions for the substrate, transistor device, and output lead before wire connection. The base metal cavity provides pre-defined mounting locations that guide wire placement, ensuring consistent positioning and reducing the complexity of achieving precise wire arrangements during assembly.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The wire connections are configured with specific geometric parameters: extending substantially perpendicular to the output lead longitudinal axis, and the first wire extending substantially perpendicular to the second wire. These defined angular and spatial parameters provide clear manufacturing targets that balance inductance minimization with achievable positioning precision.

Inventive Principle:
Principle #35Parameter changes

3Temperature

If output lead is positioned higher above substrate for thermal management, then thermal performance improves, but parasitic inductances increase due to longer wire connections

Engineering Contradiction:
Improvethermal managementVSAvoidimpedance matching
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The wires are bent into perpendicular configurations rather than extending vertically along the full height difference. This curved arrangement reduces the effective loop area and optimizes the geometric arrangement to minimize parasitic inductances even though the output lead is positioned higher for thermal management.

Inventive Principle:
Principle #14Spheroidality (Curvature)

Solution Approach 2:

Instead of allowing wires to extend vertically along the height difference, the wires are positioned to extend horizontally perpendicular to the output lead axis. This dimensional reorientation minimizes the vertical component of the wire path, reducing inductance while preserving the elevated output lead position for thermal management.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively minimizes self and mutual inductances, enhancing the performance and efficiency of RF power amplifiers by reducing impedance mismatches and improving thermal management in broadband applications.

Implementation Method 1

The shunt wire or the output wire is disposed and shaped to minimize self-inductance and to minimize mutual inductance with the shunt wire

Methodology Applied
Scientific EffectSelf-inductance minimization: Electromagnetic Induction

Implementation Method 2

The shunt wire or the output wire is disposed and shaped to minimize self-inductance and to minimize mutual inductance with the shunt wire

Methodology Applied
Scientific EffectMutual inductance minimization: Electromagnetic Induction

Data Source

PatentUS20250006688A1Output matching network to reduce self and mutual inductances of output inductive components in a cavity package
Publication Date: 2025.01.02 SUMITOMO ELECTRIC DEVICE INNOVATIONS
  • US20250006688A1 patent drawing
  • US20250006688A1 patent drawing
  • US20250006688A1 patent drawing

AI summary

A semiconductor device includes a cavity package including a substrate and at least one output lead disposed higher than the substrate, in a side view, to create a cavity. A transistor die is disposed within the cavity. A top surface of the transistor die is lower than a top surface of the output lead when viewed in the side view. A first substrate is disposed within the cavity and is separate from the transistor die. A top surface of the first substrate is lower than the top surface of the output lead in the side view. A shunt wire connects an output of the transistor die to the first substrate, and an output wire connects the output of the transistor substrate to the output lead. The shunt wire or the output wire is disposed and shaped to minimize self-inductance and to minimize mutual inductance with the shunt wire.