Cavity Semiconductor Package With Insulating Post Planarization

Solution Overview

Problem

The challenge in semiconductor packaging is to achieve a semiconductor package with improved reliability and uniform thickness, as non-uniform surface grinding of redistribution structures can lead to degraded reliability and warpage issues due to non-uniform thickness and warpage.

Innovation Solution

A semiconductor package design featuring a frame substrate with multiple wiring layers, an insulating post made of ceramic material with higher hardness than conductive bumps, and an encapsulant covering the conductive bumps and insulating post, which helps in maintaining uniform thickness and reliability by providing a grinding stop line during surface planarization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a redistribution structure is formed on a semiconductor chip to redistribute connection pads in a fan-out region, then the connection capability is improved, but the surface uniformity degrades leading to reliability degradation and thickness non-uniformity

Engineering Contradiction:

Improveredistribution layer reliabilityVSAvoidsurface uniformity

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a planarization structure (encapsulant filling the cavity) before the final redistribution layer formation. This pre-planarization step creates a uniform surface foundation that prevents subsequent thickness non-uniformity and reliability degradation, addressing the surface uniformity issue before it affects the redistribution layer quality.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements nesting by placing the semiconductor chip with its redistribution structure inside a cavity of the package substrate, then enclosing it with an encapsulant. This nested configuration allows the redistribution structure to be protected and planarized within the cavity, achieving both improved connection capability and surface uniformity.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Length of stationary object

If the semiconductor package thickness is reduced to meet miniaturization demands, then the package size is decreased, but the warpage control becomes difficult due to thickness non-uniformity

Engineering Contradiction:

Improvepackage thicknessVSAvoidwarpage control

Core Design Contradiction:

Length of stationary objectVSStability of the object's composition

Solution Approach 1:

The patent applies preliminary action by forming a planarization structure (encapsulant filling the cavity) before the final redistribution layer formation. This pre-planarization step creates a uniform surface foundation that prevents subsequent thickness non-uniformity and reliability degradation, addressing the surface uniformity issue before it affects the redistribution layer quality.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements local quality by creating a localized planarization structure (encapsulant) specifically in the region where thickness uniformity is critical. This localized approach ensures that the warpage control is enhanced precisely where needed, allowing overall package thickness reduction without compromising stability.

Inventive Principle:

Principle #3Local quality

3Volume of moving object

If the package size is reduced to meet miniaturization demands, then the package dimensions are decreased, but the manufacturing complexity increases due to precision requirements

Engineering Contradiction:

Improvepackage volumeVSAvoidmanufacturing complexity

Core Design Contradiction:

Volume of moving objectVSDevice complexity

Solution Approach 1:

The patent implements nesting by placing the semiconductor chip with its redistribution structure inside a cavity of the package substrate, then enclosing it with an encapsulant. This nested configuration allows the redistribution structure to be protected and planarized within the cavity, achieving both improved connection capability and surface uniformity.

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent applies universality by designing the encapsulant to serve multiple functions simultaneously: it acts as a planarization structure, a protective enclosure, and a structural support element. This multi-functionality reduces the need for additional separate components, thereby simplifying the manufacturing process despite the reduced package size and precision requirements.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11973042B2Semiconductor package

Publication Date: 2024.04.30 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes: a frame substrate having a plurality of wiring layers and a cavity; an adhesive member disposed at the bottom of the cavity; a semiconductor chip disposed in the cavity, with a connection pad on an upper surface and the lower surface in contact with the adhesive member; a first conductive bump disposed on the connection pad; a second conductive bump disposed on the uppermost of the plurality of wiring layers; an insulating post disposed in the cavity and whose lower surface contacts the adhesive member; an encapsulant filling the cavity and covering side surfaces of the first and second conductive bumps and the insulating post' and a redistribution structure disposed on the encapsulant, including a redistribution layer electrically connected to the first and second conductive bumps, wherein the insulating post includes a material having a greater hardness than that of the first and second conductive bumps.