Cavity Package Layout for High-Speed Chip-on-Chip Signal Integrity
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Solution Overview
Problem
Chip-on-chip (CoC) packages face challenges with signal integrity and high impedance due to bond wires, which hinder high-speed data transmission rates such as 100 Gbit/s, 400 Gbit/s, or 1.6 Tbit/s, especially in silicon photonics and optical engines that integrate electronic and photonic ICs.
Innovation Solution
The electronic device package employs a substrate with a cavity to house a photonic IC and an electronic IC, connected via a conductive through via and a fan-out package-on-package structure, reducing electrical resistance and transmission path length, and uses an encapsulant to expose specific sidewalls for efficient signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect stacked electronic components, then electrical connection is achieved, but electrical resistance increases and signal integrity deteriorates
Solution Approach 1:
The patent removes the bond wire connection method entirely and replaces it with direct die-to-die bonding. The bond wires that caused high electrical resistance and signal integrity issues are extracted from the system, and instead conductive structures are formed directly between the first and second semiconductor dies through the substrate cavity, eliminating the intermediate wire connection that caused energy loss.
Solution Approach 2:
The substrate with its conductive through vias acts as an intermediary structure that enables direct electrical connection between the stacked semiconductor dies. Instead of using bond wires as intermediaries (which caused resistance), the substrate provides conductive pathways through its through vias, serving as a low-resistance mediator for signal transmission between dies.
2Reliability
If bond wires are used for connection, then electrical communication is established, but transmission path length increases causing high impedance
Solution Approach 1:
The patent extracts and eliminates the lengthy bond wire transmission path from the system. By removing the wire bonding approach, the transmission path is shortened to direct conductive connections through the substrate and between dies, eliminating the long external wire paths that caused high impedance and signal degradation.
Solution Approach 2:
The patent transitions from a planar wire-based connection (external to the die stack) to a vertical through-substrate connection approach. Conductive structures extend vertically through the substrate cavity to establish direct electrical pathways between stacked dies, changing the connection dimension from external wire routing to internal vertical conduction paths, thereby shortening the effective transmission length.
3Adaptability or versatility
If conventional CoC package structure is used, then component integration is achieved, but warpage occurs due to CTE mismatch
Solution Approach 1:
The patent segments the package structure into distinct functional zones: a substrate cavity region for housing the first semiconductor die, and an encapsulant region for protecting the assembly. This segmentation allows independent management of thermal expansion characteristics in different regions, with the cavity providing structural support and the encapsulant accommodating CTE differences, thereby reducing overall package warpage while maintaining integration capability.
4Reliability
If encapsulant covers all sidewalls of semiconductor die, then protection is provided, but signal transmission efficiency decreases
Solution Approach 1:
The patent applies local quality by selectively exposing specific sidewalls of the first semiconductor die that are required for signal transmission, while leaving other sidewalls covered by the encapsulant for protection. This localized approach ensures that signal pathways remain accessible and efficient, while still providing comprehensive protective encapsulation for portions of the die that do not require signal exchange, thus balancing protection and transmission efficiency.
Data Source
AI summary
An electronic device package includes a substrate, a first semiconductor die, a second semiconductor die and an encapsulant. The substrate includes a first surface, and a second surface opposite to the first surface. The substrate defines a cavity recessed from the first surface. The first semiconductor die is disposed in the cavity. The second semiconductor die is disposed over and electrically connected to the first semiconductor die. The encapsulant is disposed in the cavity of the substrate. The encapsulant encapsulates a first sidewall of the first semiconductor die, and exposes a second sidewall of the first semiconductor die.