Cavity-Based Protection for Vertical Stack Intermediate Layers
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Solution Overview
Problem
Existing methods for protecting bevelled peripheral edges in semiconductor wafers during thinning processes either expose metallization levels, leading to contamination or are limited to vertically cut edges, causing defects and equipment contamination.
Innovation Solution
A method involving the formation of cavities in intermediate layers, followed by conformal deposition and selective removal of protection material, ensuring targeted protection without covering non-requiring layers, using a dielectric material to prevent contamination and defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conformal layer of insulating material is deposited on the unassembled surface and walls to protect exposed copper, then contamination is prevented, but layers not requiring protection are coated causing mechanical stress defects
Solution Approach 1:
The patent applies local quality by selectively depositing protection material only in the cavity where it is needed to protect the intermediate layer, rather than conformally coating all surfaces. The deposition is localized to the cavity region, leaving other areas unaffected and avoiding unnecessary mechanical stress on unprotected layers.
2Strength
If bevelled peripheral parts are mechanically cut away prior to thinning, then fracture during thinning is prevented, but exposed metallization levels contaminate equipment and substrate
Solution Approach 1:
The patent introduces an intermediary protection material that fills the cavity formed after removing bevelled peripheral parts. This material acts as a mediator between the exposed intermediate layer and the external environment, preventing contamination while allowing the trimming operation to proceed. The protection material is subsequently removed after serving its protective function.
3Object-affected harmful factors
If lateral protections are formed as spacers around transistor gates, then peripheral parts are protected, but the method is only applicable to vertically cut edges
Solution Approach 1:
The patent transitions from two-dimensional planar spacer protections to a three-dimensional cavity-based protection approach. By forming a cavity that extends from the surface into the intermediate layer and filling it with protection material, the method becomes adaptable to various edge orientations and cut angles, not limited to vertical edges only.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively protects the intermediate layers by preventing contamination and reducing defects, allowing for efficient trimming of bevelled edges without exposing metallization levels, thus maintaining equipment cleanliness and improving process robustness.
Implementation Method 1
a conformal and continuous deposition of a protection material on the free face and in the cavity
Implementation Method 2
the formation of the cavity in the intermediate layer may comprise a selective chemical etch. Thus, the etching of the intermediate layer may not require any etch mask formed by a photolithographic step
Data Source
AI summary
A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed.