Cavity Resonator Antenna Integration in Semiconductor Packages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packaging technologies face challenges with antenna solutions that increase footprint and z-height, leading to reduced efficiency due to distance losses between antennas and integrated circuits, especially as carrier frequencies increase, necessitating a more compact and efficient antenna solution.
Innovation Solution
Integration of cavity resonator antennas directly on the transceiver chip within semiconductor packages, utilizing a conductive cavity with interconnects and a conductive lid to minimize feed line distances and enhance signal transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If antennas are implemented into printed circuit boards or device housings, then wireless communication functionality is achieved, but the footprint and z-height of the PCB and device increase
Solution Approach 1:
The patent merges the antenna with the semiconductor package substrate, integrating the antenna structure directly into the package rather than implementing it separately in the PCB or device housing. This consolidation eliminates the need for additional antenna space on the PCB, thereby reducing the overall footprint while maintaining wireless communication functionality.
Solution Approach 2:
The patent utilizes the z-height dimension of the semiconductor package by positioning the antenna in the vertical direction above the substrate. This three-dimensional integration allows the antenna to be formed within the package volume rather than requiring additional planar space, thus reducing the footprint while achieving the required antenna functionality.
2Reliability
If antennas are implemented into printed circuit boards or device housings, then wireless communication functionality is achieved, but the z-height of the PCB and device increases
Solution Approach 1:
The patent merges the antenna with the semiconductor package substrate, integrating the antenna structure directly into the package rather than implementing it separately in the PCB or device housing. This consolidation eliminates the need for additional antenna space on the PCB, thereby reducing the overall footprint while maintaining wireless communication functionality.
3Reliability
If antennas are implemented into printed circuit boards or device housings, then wireless communication functionality is achieved, but losses increase due to distances between antennas and integrated circuits
Solution Approach 1:
The patent merges the antenna with the semiconductor package substrate, integrating the antenna structure directly into the package rather than implementing it separately in the PCB or device housing. This consolidation eliminates the need for additional antenna space on the PCB, thereby reducing the overall footprint while maintaining wireless communication functionality.
Solution Approach 2:
The patent segments the semiconductor package into functional regions, dedicating specific areas of the substrate to antenna elements while other areas house the integrated circuit. This segmentation allows the antenna to be positioned in optimal locations for signal transmission while maintaining close proximity to the IC, thereby reducing signal losses.
4Productivity
If carrier frequency is increased to improve data throughput, then communication performance improves, but losses scale with frequency and increase
Solution Approach 1:
The patent merges the antenna with the semiconductor package substrate, integrating the antenna structure directly into the package rather than implementing it separately in the PCB or device housing. This consolidation eliminates the need for additional antenna space on the PCB, thereby reducing the overall footprint while maintaining wireless communication functionality.
Solution Approach 2:
The patent optimizes the antenna geometry and dimensions to be appropriate for high-frequency operation. By scaling the antenna features to match the wavelength at the operating frequency and adjusting the antenna structure parameters, the patent enables efficient operation at higher carrier frequencies while minimizing frequency-dependent losses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces signal losses and minimizes space consumption, enabling more efficient communication and data throughput while maintaining compact form factors, particularly beneficial for high-frequency applications like terahertz devices.
Implementation Method 1
a cavity resonator antenna over the first conductive layer and the substrate, wherein the cavity resonator antenna includes a conductive cavity, a cavity region, and a plurality of interconnects
Implementation Method 2
the conductive cavity extends vertically from the first conductive layer to the second conductive layer, wherein the cavity region is embedded with the conductive cavity, the first conductive layer, and the second conductive layer
Data Source
AI summary
Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a cavity resonator antenna over the first conductive layer and substrate. The cavity resonator antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the cavity resonator antenna, first conductive layer, and substrate. The conductive cavity may extend vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects. The first interconnects may include through-mold vias (TMVs), through-silicon vias (TSVs), conductive sidewalls, or conductive trenches.