Cavity-Based Semiconductor Device for Parasitic Capacitance Reduction
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Solution Overview
Problem
The scaling of channel length in MOSFETs leads to significant short-channel effects, such as performance degradation, increased power consumption, and signal-to-noise ratio decrease, which conventional technologies struggle to address effectively, particularly due to challenges in controlling the thickness of the silicon layer and gate leakage currents in 3-dimensional device structures.
Innovation Solution
A semiconductor device with a cavity in the semiconductor base, allowing for increased distance between gates and source/drain regions, reducing parasitic capacitance and resistance, and incorporating a channel layer and mask layer to enhance carrier mobility, along with epitaxial growth of source/drain regions to adjust stress and mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length is scaled down to improve device integration and speed, then device density and operating speed are improved, but short-channel effects become significant causing performance degradation
Solution Approach 1:
The patent transitions from a conventional planar structure to a 3-dimensional structure where the gate wraps around the channel region. This dimensional change allows the gate to control the channel from multiple directions (top and sides), providing superior electrostatic control over the depleted region and effectively suppressing short-channel effects even at scaled dimensions.
Solution Approach 2:
The patent segments the channel region into multiple portions by introducing a depleted region that divides the channel. This segmentation allows independent control of different channel sections, enabling better management of short-channel effects while maintaining scaled dimensions for high-speed operation.
2Reliability
If more impurities are introduced into the channel to control short-channel effects, then short-channel effects are suppressed, but carrier mobility decreases and impurity distribution becomes uncontrollable
Solution Approach 1:
The patent extracts the impurity-containing regions (source and drain) from the channel region by introducing a depleted region between them. This spatial separation prevents impurity diffusion into the channel, maintaining clean channel regions with controlled impurity distributions while still achieving short-channel effects suppression through the depleted region geometry.
3Speed
If the thickness of gate oxide dielectric is reduced to improve device speed, then device speed is improved, but gate leakage currents increase
Solution Approach 1:
The patent employs a composite gate structure with a gate dielectric layer and a gate electrode, where the gate dielectric can be composed of multiple layers including high-k materials. This composite structure allows for thinner effective oxide thickness to improve speed while using high-k materials to reduce leakage currents by providing higher dielectric constant with greater physical thickness.
4Reliability
If source/drain region edges are extended to reduce resistance, then source/drain resistance is reduced, but parasitic capacitances increase leading to increased resistance-capacitance delay
Solution Approach 1:
The patent extends source/drain regions in the vertical dimension by creating elevated source/drain structures that rise above the substrate plane. This 3-dimensional extension reduces the horizontal footprint required for achieving low resistance, thereby reducing parasitic capacitances to adjacent gates while maintaining low resistance through increased vertical cross-sectional area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance and source/drain resistance, alleviates short-channel effects, and enhances carrier mobility by increasing the cross-sectional area and adjusting stress in the channel region, thereby improving device performance.
Implementation Method 1
incorporating a channel layer and mask layer to enhance carrier mobility, along with epitaxial growth of source/drain regions to adjust stress and mobility
Data Source
AI summary
The invention provides a semiconductor device, including: a semiconductor base, on an insulation layer; source/drain regions abutting opposite first sides of the semiconductor base; and gates at opposite second sides of the semiconductor base, wherein the semiconductor base includes a cavity, and the insulation layer is exposed by the cavity. The invention also provides a method for forming a semiconductor device, including: forming a semiconductor bottom on an insulation layer; forming source/drain regions, the source/drain regions abutting opposite first sides of the semiconductor bottom; forming gates on opposite second sides of the semiconductor bottom; and removing a part of the semiconductor bottom to form a cavity in the semiconductor bottom, the cavity exposing the insulation layer. With the technical solutions provided by the invention, short-channel effects can be alleviated, and the resistance of the source/drain regions and parasitic capacitance can be reduced.