Semiconductor Chip Package With Cavity Substrate
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Solution Overview
Problem
Current semiconductor chip packages face challenges in achieving high integration density and reduced thickness while maintaining reliable electrical interconnections for high-speed operation in miniaturized electronic devices.
Innovation Solution
The solution involves a semiconductor chip package design with a substrate having a cavity and a patterned layer of electrically conductive material for internal or external interconnection patterns, where the chip is mounted in a flip-chip orientation with conductive vias or bumps for reliable bonding, and a method of fabricating such packages using substrates with interconnection patterns and adhesive layers for stacked configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chip packages are stacked to increase integration density, then the number of chips per package increases, but the overall thickness reduction becomes more difficult
Solution Approach 1:
The patent embeds chips within cavities formed in the substrate, creating a nested structure where chips are positioned inside recesses rather than on flat surfaces. This nesting approach allows multiple chips to be stacked vertically while minimizing the increase in overall package thickness, as chips are housed within the substrate volume rather than adding full chip thickness to the package height.
Solution Approach 2:
The patent transitions from two-dimensional chip arrangement on a flat substrate to three-dimensional stacking within cavity structures. By utilizing the vertical dimension and creating multi-level cavity arrangements, the package achieves higher integration density while controlling thickness through strategic use of substrate depth rather than simply stacking chips end-to-end.
2Length of stationary object
If the package thickness is reduced for miniaturization, then the form factor improves, but the reliability of electrical interconnections deteriorates
Solution Approach 1:
The patent forms conductive vias and interconnection patterns within the substrate before chip mounting. This preliminary preparation of electrical pathways ensures that interconnection reliability is established through pre-formed, structurally sound conductive paths that are integrated into the substrate architecture, rather than relying on post-assembly wire bonding or surface-mounted connections that may be more susceptible to failure in thin packages.
Solution Approach 2:
The patent replaces traditional wire bonding mechanical interconnection methods with direct conductive via connections embedded in the substrate. This substitution eliminates the need for separate wire bonding processes and creates more robust electrical connections that are mechanically integrated into the package structure, improving reliability while maintaining reduced thickness.
3Ease of manufacture
If traditional wire bonding is used for electrical interconnection, then the process is well-established, but the package thickness increases and high-speed operation becomes difficult
Solution Approach 1:
The patent replaces wire bonding with direct conductive connections through substrate-integrated vias and trace patterns. This substitution eliminates the mechanical wire bonding process entirely, creating direct electrical pathways that reduce signal path length and inductance, thereby enabling high-speed operation while simplifying the manufacturing process by eliminating separate wire bonding equipment and steps.
Solution Approach 2:
The patent extracts the wire bonding function entirely from the package assembly process. Instead of adding wire bonding as a separate manufacturing step, the electrical interconnection function is integrated directly into the substrate fabrication process through pre-formed conductive vias and traces, eliminating the need for wire bonding equipment and processes while achieving superior electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in a thin, highly reliable semiconductor package with high integration density, enabling high-speed operation without the need for wire bonding, thus addressing the limitations of existing technologies.
Implementation Method 1
an adhesive interlayer coupling the first and second sub-substrates together
Implementation Method 2
a patterned layer (at least one) of electrically conductive material constituting an internal interconnection pattern
Implementation Method 3
electrically conductive vias are disposed in the holes, respectively, and the pads of the semiconductor chip are electrically conductively bonded to the vias, respectively
Data Source
AI summary
According to an example embodiment, a semiconductor chip package includes a substrate comprising a substrate body having a first main surface, a second main surface, and a cavity that defines an opening in the first main surface, and a layer of electrically conductive material integral with the substrate body. The layer of electrically conductive material constitutes an interconnection pattern of the substrate. The semiconductor chip packages further includes a semiconductor chip disposed within the cavity and mounted to the substrate. The chip includes electrical contacts in the form of pads and the pads face in a direction towards the bottom of the cavity such that the chip has a flip-chip orientation with respect to the substrate. The pads are electrically conductively bonded to respective portions of the interconnection pattern.