Cavity Thermal Stack in Package-on-Package for Direct Heat Conduction

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Solution Overview

Problem

Current package-on-package (PoP) systems lack effective thermal solutions to manage heat transfer between processor and memory packages, leading to inadequate thermal performance and potential overheating.

Innovation Solution

Embedding a thermal stack within a cavity in the PoP substrate provides a direct thermal pathway between the packages, reducing the number of thermal interfaces and optimizing thermal conduction by using a combination of thermal interface materials and thermally conductive substrates, such as copper and silicon, to balance heat transfer in various directions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If an air-gap is used between the memory package and the mold layer of the processor package, then the structural simplicity is maintained, but the thermal conduction performance deteriorates

Engineering Contradiction:
Improvestructural simplicityVSAvoidthermal conduction performance
Core Design Contradiction:
Device complexityVSTemperature

Solution Approach 1:

The patent removes the air-gap between the memory package and processor package mold layer, extracting the thermal barrier element to enable direct thermal contact and improve heat transfer efficiency

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs composite thermal interface materials with varying thermal conductivities at different locations to optimize heat transfer while maintaining structural integrity, using materials such as copper, aluminum, and thermally conductive polymers in combination

Inventive Principle:
Principle #40Composite materials

2Temperature

If direct thermal coupling is implemented between processor and memory packages, then thermal conduction is improved, but the thermal load on memory dies increases

Engineering Contradiction:
Improvethermal conductionVSAvoidthermal load on memory dies
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent implements spatially varying thermal conductivity in the thermal interface material, with higher thermal conductivity regions positioned to conduct heat away from processor dies and lower thermal conductivity regions that prevent excessive heat transfer to memory dies, creating a gradient structure that optimizes thermal management

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces a thermal interface material as an intermediary substance between the processor and memory packages that mediates heat transfer, controlling the thermal coupling strength to improve processor cooling while protecting memory dies from excessive thermal load

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances thermal performance by reducing thermal interfaces and optimizing heat management, preventing overheating and improving the overall thermal efficiency of the system.

Implementation Method 1

thermal stack embedded in a cavity in the PoP substrate... provides a direct thermal pathway between the dies of the memory package and the dies of the processor package... optimizing thermal conduction

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

optimizing thermal conduction by using a combination of thermal interface materials and thermally conductive substrates, such as copper and silicon, to balance heat transfer in various directions

Methodology Applied
Scientific EffectHeat transfer: Conduction (thermal)

Data Source

PatentUS11769753B2Thermally-optimized tunable stack in cavity package-on-package
Publication Date: 2023.09.26 INTEL CORP
  • US11769753B2 patent drawing
  • US11769753B2 patent drawing
  • US11769753B2 patent drawing

AI summary

Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.