Cavity Wafer Stabilization for TSV Interposer Warpage
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Solution Overview
Problem
Conventional flip chip stacking methods suffer from TSV interposer warpage, which affects IC performance and assembly yield, and thermo-compression bonding leads to issues like flux residue and uneven heat profiles, resulting in poor soldering performance.
Innovation Solution
The method involves forming a cavity or support wafer with cavities and corner guides to mechanically stabilize the TSV interposer, applying a vacuum or removable glue to hold it in place, and then bonding the integrated circuit die to the TSV interposer using reflow joining, followed by underfilling and bonding the solder bumps to an organic substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional flip chip stacking methods are used, then the process is simple, but TSV interposer warpage occurs which affects IC performance and assembly yield
Solution Approach 1:
A cavity wafer is introduced as an intermediary component during the flip chip stacking process. The cavity wafer provides mechanical support to the TSV interposer during assembly, preventing warpage. After assembly, the cavity wafer is removed, leaving the stabilized interposer structure. This intermediary solves the warpage problem without permanently complicating the final product structure.
Solution Approach 2:
The cavity wafer is prepared in advance with pre-formed cavities and corner guides before the TSV interposer is placed on it. This preliminary preparation ensures that the interposer is immediately supported in the correct position and orientation, preventing warpage from occurring during the assembly process itself.
2Reliability
If thermo-compression bonding is used to mitigate TSV interposer warpage, then warpage is reduced, but flux residue and uneven heat profiles occur resulting in poor soldering performance
Solution Approach 1:
The invention replaces thermo-compression bonding with a mechanically-supported assembly process. Instead of using heat and pressure to mitigate warpage, the cavity wafer provides mechanical support to prevent warpage. This substitution eliminates the flux residue and uneven heat profile problems associated with thermo-compression bonding while maintaining effective warpage mitigation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces TSV interposer warpage, improving IC die performance and assembly yield by providing mechanical stabilization during the stacking process and enhancing soldering performance.
Implementation Method 1
applying a vacuum to the bottom surface of the cavity wafer to hold the TSV interposer with solder bumps in place relative to the cavity wafer
Implementation Method 2
performing reflow joining to attach the integrated circuit die to the other surface of the TSV interposer
Implementation Method 3
bonding the solder bumps of the stacked interposer unit to an organic substrate
Implementation Method 4
the act of removing the stacked interposer unit comprises performing chemical dissolution
Data Source
AI summary
A method for flip chip stacking includes forming a cavity wafer comprising a plurality of cavities and a pair of corner guides, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit, removing the stacked interposer unit from the cavity wafer, and bonding the solder bumps of the stacked interposer unit to an organic substrate such that the stacked interposer unit and the organic substrate form a flip chip.