CAVLC Encoder Circuit Parallel Run Before Syntax Encoding
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Solution Overview
Problem
Conventional CAVLC encoding methods in H.264 suffer from reduced throughput due to sequential encoding of run before syntax elements and coefficients, which negatively impacts bitrate maintenance and performance.
Innovation Solution
A method and apparatus that simultaneously encode run before syntax elements with coefficients, utilizing a control circuit and encoder circuit to perform look-up table operations, zeros left tracking, and barrel shifting in parallel, thereby increasing cycle throughput and maintaining a given bitrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CAVLC encoding is performed sequentially (coefficients first, then run before syntax elements), then encoding accuracy is maintained, but throughput is reduced and cycle time increases
Solution Approach 1:
The patent performs preliminary calculations of run before values during the coefficient encoding phase itself, rather than waiting for sequential processing. The encoder calculates run before syntax element values in advance while processing coefficients, storing them for immediate output, thereby eliminating the need for a separate encoding pass and doubling throughput
Solution Approach 2:
The patent merges the encoding of coefficients and run before syntax elements into a single unified processing operation. By combining these previously separate sequential operations into one parallel process, the encoder achieves doubled throughput while maintaining accurate bitrate control through integrated look-up table operations
2Productivity
If run before encoding is performed sequentially after coefficient encoding, then encoding precision is maintained, but device utilization and performance are reduced
Solution Approach 1:
The patent segments the encoding process into independent parallel operations: coefficient encoding, run before calculation, and syntax element output all occur simultaneously as separate but coordinated tasks within the same encoding cycle, rather than as sequential steps
Solution Approach 2:
The patent changes the temporal parameters of the encoding process by calculating run before values during coefficient processing rather than afterward. This parameter change in processing timing enables parallel execution and doubles throughput while the look-up table structure manages the complexity of coordinating multiple operations
3Reliability
If conventional sequential CAVLC encoding is used, then bitrate control is maintained, but encoding speed and performance are negatively affected
Solution Approach 1:
The patent implements feedback mechanisms through integrated look-up table operations that continuously monitor and adjust encoding parameters during the parallel processing of coefficients and run before syntax elements, ensuring accurate bitrate control is maintained even as encoding speed doubles
Solution Approach 2:
By performing preliminary run before calculations during coefficient encoding with immediate look-up table operations, the system maintains accurate bitrate control through real-time feedback while doubling encoding speed, as both operations occur in the same processing cycle rather than sequentially
Data Source
AI summary
An apparatus including a control circuit and an encoder circuit. The control circuit may configured to generate a first control signal and a second control signal. The encoder circuit may be configured to (i) receive a plurality of coefficients, the first control signal and the second control signal and (ii) generate an encoded signal in response to the plurality of coefficients, the first control signal and the second control signal. The encoder circuit may be further configured to simultaneously encode run before syntax elements with the plurality of coefficients.