CBiCMOS Emitter Structure Protection via Segmented Masking
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Solution Overview
Problem
The manufacturing of complementary bipolar CMOS transistors requires a high number of mask and etch steps, which increases costs and cycle time, and combining extrinsic base implants with source/drain implants can lead to counter-doping of the emitter, increasing resistance and affecting DC and AC performance.
Innovation Solution
A protective layer is formed over the emitter structure, and lateral portions are etched to form the emitter structure, followed by an oxide layer deposition and etchback process, allowing for the extrinsic base implant without damaging the emitter, and then the protective layer is removed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the extrinsic base implants and source/drain implants are combined during the manufacturing process, then the mask count is reduced, but counter-doping of the emitter occurs which increases resistance and adversely affects DC and AC performance
Solution Approach 1:
The patent divides the emitter region into two distinct zones: a protected central region and exposed lateral regions. The protective layer is selectively removed laterally to allow base implantation in specific areas while preserving the central emitter region from counter-doping. This segmentation enables simultaneous base and source/drain implantation without compromising emitter performance.
Solution Approach 2:
A protective layer (nitride or oxide) is introduced as an intermediary material between the implantation process and the emitter structure. This protective layer acts as a barrier that prevents counter-doping of the emitter during base implantation, while still allowing the process to proceed with combined implants. The protective layer is subsequently removed to complete the structure.
2Reliability
If a resist block is placed over the emitter during source/drain implant to protect it, then counter-doping is prevented, but the emitter self-alignment is compromised because the resist block must be smaller than the emitter
Solution Approach 1:
The protective layer serves as an intermediary that provides superior protection compared to traditional resist blocks. Unlike resist that requires precise sizing to maintain self-alignment, the protective layer can be deposited conformally and selectively removed, providing robust protection while maintaining alignment through the self-aligned nature of the deposition and etchback processes.
Solution Approach 2:
The protective layer is deposited beforehand (prior to implantation) and then selectively removed through etchback to expose only the lateral portions needed for base implantation. This preliminary protective action ensures the emitter is protected during implantation while the selective removal maintains self-alignment, eliminating the need to compromise resist block dimensions.
3Reliability
If the protective layer is used to protect the emitter during implantation, then counter-doping is prevented, but additional process steps (oxide deposition and etchback) are required
Solution Approach 1:
The protective layer deposition and subsequent etchback steps are merged with existing process sequences in the CBiCMOS manufacturing flow. The oxide layer deposition is combined with other dielectric deposition steps, and the etchback is integrated with other planarization or patterning steps, thereby minimizing the net increase in process complexity while achieving superior emitter protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the mask count, preventing counter-doping and maintaining emitter self-alignment, thereby improving the DC and AC performance of the transistor without increasing manufacturing steps.
Implementation Method 1
The protective layer protects the emitter structure from the effects of the implant process
Implementation Method 2
lateral portions of the protective layer and the emitter layer are etched to form an emitter structure
Implementation Method 3
An oxide layer is then deposited over the transistor structure
Implementation Method 4
A source/drain implant process is then performed to implant an extrinsic base region of the transistor
Data Source
AI summary
A system and method are disclosed for manufacturing an emitter structure in a complementary bipolar complementary metal oxide semiconductor (CBiCMOS) transistor manufacturing process. A protective layer is formed over an emitter layer in a transistor structure and lateral portions of the protective layer and the emitter layer are etched to form an emitter structure. An oxide layer is then deposited over the transistor structure and an etchback process is performed to remove portions of the oxide layer from the top of the protective layer. A source/drain implant process is then performed to implant an extrinsic base region of the transistor. The protective layer protects the emitter structure from the implant process. Then the protective layer is removed from the emitter structure.