CBRAM DRAM Memory Architecture for Low Power Save Restore
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Solution Overview
Problem
Conventional memory systems face challenges in achieving fast and low-energy save/restore operations due to the limitations of DRAM and Flash memory, including high power consumption and slow data transfer rates, especially in mobile devices, where standby power and latency are critical concerns.
Innovation Solution
Incorporating a solid electrolyte layer-based conductive bridging random access memory (CBRAM) that operates at similar voltages to DRAM, enabling high-bandwidth data transfer between volatile and nonvolatile memory sections, allowing for faster and more energy-efficient save and restore operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is copied from DRAM to Flash memory when entering standby mode, then data is preserved in nonvolatile memory, but system power consumption increases and latency is added
Solution Approach 1:
The patent combines DRAM and CBRAM into a single memory system where CBRAM cells are integrated alongside DRAM cells. This merging allows the system to maintain volatile memory functionality while incorporating nonvolatile capabilities, eliminating the need for separate Flash memory operations and reducing overall power consumption during save/restore cycles.
Solution Approach 2:
CBRAM serves as an intermediary between DRAM and traditional Flash memory. It provides nonvolatile storage capabilities with DRAM-like speed and low voltage operation, acting as a mediator that eliminates the need for high-voltage Flash programming while maintaining data persistence during standby mode.
2Reliability
If data is copied from DRAM to Flash memory, then data is saved for restore operations, but data transfer speed is slow
Solution Approach 1:
By merging CBRAM cells with DRAM cells in the same memory structure, the patent enables direct, high-speed data transfer between volatile and nonvolatile storage without the slow Flash programming process. The integrated architecture allows bit-to-bit copying at DRAM speeds.
Solution Approach 2:
The patent changes the physical parameters of the memory system by introducing CBRAM cells that operate at DRAM-compatible voltages and speeds. This parameter change enables fast data transfer while maintaining nonvolatile persistence, unlike traditional Flash memory which operates at higher voltages and slower speeds.
3Reliability
If SONOS elements are used for nonvolatile storage, then data can be retained without power, but high voltages are required for programming
Solution Approach 1:
The patent changes the voltage parameter by using CBRAM cells that operate at the same low voltages as DRAM, eliminating the need for high-voltage programming required by SONOS and Flash memory. This enables nonvolatile storage without the power and integration challenges of high-voltage technologies.
Solution Approach 2:
CBRAM acts as an intermediary technology that bridges the gap between low-voltage DRAM and high-voltage Flash/SONOS. It provides nonvolatile capabilities compatible with standard DRAM voltage levels, eliminating the need for complex high-voltage generation circuits.
4Reliability
If SRAM cells are paired one-to-one with SONOS elements, then data can be copied bit-to-bit, but configuration flexibility is lost
Solution Approach 1:
The patent implements a universal memory architecture where CBRAM cells can serve multiple functions: nonvolatile storage, volatile storage, and data transfer buffer. The memory system can dynamically configure which regions operate in which mode, providing flexibility that hardwired SRAM-SONOS pairings cannot achieve.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
CBRAM technology enhances standby power management and reduces latency by enabling rapid data transfer and storage with lower power consumption compared to traditional systems, facilitating more aggressive save/restore operations without the need for additional nonvolatile memory like Flash.
Implementation Method 1
A memory device can include a volatile section and a CBRAM section. The CBRAM section can include a solid electrolyte layer
Data Source
AI summary
A system can include a first memory section comprising a plurality of volatile memory cells; a second memory section comprising a plurality of nonvolatile memory cells; a first data path configured to transfer data between the first and second memory sections; an interface circuit coupled to receive access commands and address values, the interface circuit configured to determine if a data transfer operation is occurring in the device, and if the data transfer operation is occurring, accessing the address in the first memory section or accessing a location in the second memory section based on a select value, and if the data transfer operation is not occurring, accessing the address in the first memory section; and a compare circuit configured to compare a received address to a predetermined value to generate the select value.