Comparator-Based Switched-Capacitor Offset Compensation for Delay Error
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Solution Overview
Problem
Comparator based switch capacitor circuits suffer from errors due to circuit delay, resulting in inaccuracies in the final sampled values.
Innovation Solution
Introducing an offset voltage to the comparator, which is calibrated to cancel out the error caused by circuit delay, allowing for precise charge transfer between capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a comparator based switch capacitor circuit is used for charge transfer, then the circuit speed and integration are improved, but error due to circuit delay increases
Solution Approach 1:
The patent applies preliminary anti-action by introducing an offset voltage to the comparator that pre-compensates for the circuit delay error. The offset voltage is calibrated to generate an error signal equal in magnitude but opposite in sign to the delay-induced error, thereby canceling it out before it affects the final sampled value. This allows the circuit to maintain high speed operation while achieving accurate sampling results.
2Productivity
If circuit delay is present in the charge transfer phase, then the circuit operates faster, but the final sampled value contains error
Solution Approach 1:
The patent implements feedback by using the offset voltage to generate an error signal that is fed back to correct the sampling accuracy. The calibration circuit measures the actual error caused by circuit delay and adjusts the offset voltage accordingly, creating a closed-loop system that continuously compensates for delay effects. This feedback mechanism enables the circuit to maintain both high productivity and precision.
3Measurement precision
If offset voltage is introduced to the comparator, then sampling accuracy is improved, but circuit complexity increases
Solution Approach 1:
The patent applies parameter changes by adjusting the offset voltage parameter of the comparator to optimize sampling accuracy. Rather than adding complex hardware components, the solution modifies an existing electrical parameter (the offset voltage) that can be calibrated and adjusted. This approach improves precision while minimizing increases in circuit complexity, as the offset voltage can be implemented through simple voltage reference circuits.
Data Source
AI summary
An error reducing comparator based switch capacitor (CBSC) circuit comprises: a comparator of a substantial offset, a charge pump controlled by an output of the comparator, and a plurality of capacitors. The CBSC circuit cyclically operates through a sampling phase, and a transfer phase. During the sampling phase, an input voltage is sampled by a first capacitor. During the transfer phase, the charge stored on the first capacitor is transferred to a second capacitor through injecting or draining charge using the charge pump. The amount of the offset is properly set to reduce an error due to circuit delay of the CBSC circuit.